xc6lx45

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Everything posted by xc6lx45

  1. xc6lx45

    SPI TFT Display

    Right... sorry, didn't read the last line of your original post.
  2. xc6lx45

    SPI TFT Display

    Hi, one option - depending on your needs - is to simply hook up a regular VGA monitor via the RGB cable. Actually, jumper cables with female ends can be plugged right into to a 15-pin sub-D connector. A 40x20 monochrome text display fits into the smallest block RAM, needs three pins (HSYNC, VSYNC and e.g. GREEN) and looks very much like 1979...
  3. xc6lx45

    Zybo or Zybo-Z7 for MIPI CSI-2 experimentation?

    This is interesting... There was one simple question: Whether inputs can be configured to a lower voltage even though the IO bank is driven from a higher voltage. I've done that successfully with MIPI RFFE on Spartan 6. So yes, I guess it works for single-ended signals, at least in ISE (by setting the IO standard to LVCMOS18 in my application). Later, found the FMC Carrier S6 board, which has FPGA-selectable IO voltages. But that's history. But D-PHY to RFFE is like jet fighter to paper plane.. Back then, we did some studies of driving another D-PHY based standard straight from an FPGA, and concluded that it isn't possible without additional mixed signal circuitry aka "PHY chip", for "electrical" reasons suspiciously similar to the ones stated above.
  4. xc6lx45

    Troubleshooting Switch Issues on FPGA

    Hi, if I were faced with the issue (this is maybe somewhat overkill) , I'd set up a five-line design that routes two switches (one known-good) to two LEDs. Then build and run twice, with pullups or pulldowns enabled in the constraints file for the switch input set_property PULLDOWN true [get_ports {mySwitchPorts[*]}] same alterrnatively with PULLUP If the LED follows the pull direction on the broken switch, the pin is floating. This would indicate a bad solder connection or a torn PCB trace / via. Sometimes, pushing gently with a finger on PCB and FPGA can reveal such a failure. Disclaimer: 99.9 % of all isses are NOT hardware-related (but that makes the remaining 0.1 % all the harder to spot)
  5. xc6lx45

    Problem with Basys 3 XADC Ip Core

    Hi, I'm happy to hear that it works. But, note that there is no "Vp/Vn" channel. The ADC has 16 AUX inputs that can be multiplexed to one of the two ADC cores. I think what you did now was to read the value from the results register that belongs to the channel that is being triggered. My proposal was to switch the ADC to the AUX input that is physically connected. Once you use more than one channel, this can't be avoided. A "for" loop should get some data, but then your code becomes very brittle, timing-wise. Any interrupt that distracts the CPU for a microsecond will cause you to skip a sample. I suspect you will have a hard time with a concept, where software is timing-critical. The easier way would be IMHO to use event-triggered mode via the XADC's CONVST pin, and a hardware FIFO.
  6. Hi, for the cascaded shift registers, you don't need to add anything. Once two stages work cleanly [*], you can cascade an infinite number and it'll still work (clock distribution is the bottleneck in reality). That's the beauty of synchronous design. BTW you will find 74595 variants that are much faster. I've seen one (SMD) double-trigger on a 3 ns reflection on an unterminated cable... That would be the equivalent to 300 MHz... I run mine at 30M. [*] the theory isn't rocket science, but it does cause the occasional headache.
  7. xc6lx45

    Invalid value for CLKIN1_PERIOD in PLLE2_BASE

    I think Hamster is right. I had to use MMCM for a 12 MHz crystal, PLL doesn't work. The easiest way to fix this is in Vivado, Flow navigator window on the left under "Project manager": "IP Catalog". Enter "clk" into the search window, pick "Clocking wizard" under "FGPA features and clocking", "clocking". Select "Primitive": MMCM (should be default), enter "Primary input clock": 12 (Megahertz). Set the output frequency, disable unused inputs and outputs such as reset (fewer warnings later) and click "generate". The "component name" on the top, e.g. "clk_wiz_0", is used for instantiation. Oh, and you should probably comment out the "create_clock" line in the constraints file, because the frequencies are now set by the clocking IP. Otherwise Vivado will start analyzing interactions between "alternative" clocks that don't exist.
  8. xc6lx45

    Problem with Basys 3 XADC Ip Core

    I think you need to set the channel for conversion. See here https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf Table 3-4 and Table 3.7, register 0x40 bits 0 .. 4. I'm not familiar with the wrapper functions, but they couldn't guess beforehand, which one of the 16 AUX channels you want to read. So it needs to be set.
  9. xc6lx45

    Problem with Basys 3 XADC Ip Core

    Where are you setting the VCCINT channel for "single channel conversion"? This needs to be done before while(1){ //wait until EOS activated
  10. xc6lx45

    AD2 scope voltage inaccuracy

    Hi, I suspect you are observing the so-called "Gibbs Phenomenon". If I throw in more bandwidth to represent a signal, the overshoot actually gets worse. But, the duration of the peaks shortens at the same time, so the overall approximation still becomes more accurate in terms of energy / power. Nature is playing tricks at us and this guy is laughing from his grave. In other words, the result depends strongly on the characteristics of the instrument, not the signal itself. Your 10 % PWM signal is nasty because its spectrum is so wide. Here is how it looks in calculation: I've drawn an arbitrary line at -20 dB, which isn't particularly accurate but rougly corresponds to the ~10 % voltage error you're observing. Only the 19th harmonic drops below that line. Here is the same again, with the pulse width at 50 % - a regular square wave.The spectrum is much friendlier, with most of the energy in the fundamental: To sum this up, the "peaks" of your test signal are not well defined. Try using the calibration output from the KS scope as a test signal, it should have adequate filtering (at least suitable for the KS instrument). A sine wave avoids the problem altogether. Calculation, if anybody is interested (Octave / Matlab): close all; sig = zeros(1, 1000); sig(1:500/10)=1; sig = repmat(sig, 1, 1234); figure(); q=20*log10(eps+abs(fft(sig))); h=plot((0:numel(q)-1)/1234, q-(q(1+1*1234))); xlabel('harmonics #'); ylabel('dB'); grid on
  11. xc6lx45

    CMOD A-7

    Hi, have a look at this on the Xilinx forum: https://www.xilinx.com/support/answers/23277.html "... where the various I/Os of the different Virtex/Spartan families have been shorted to Ground or VCC with outputs programmed for strongest drive strength..This condition has been maintained over days and weeks with no latent damage seen" Well, the article was written well before 28 nm came out, but it's up to interpretation anyway since they don't promise anything. I'd suggest to use common sense, and not lose sleep over a $50 component. Save that for the $3500 board that has +12V 3A on FMC connectors... a slipped probe will blow the whole IO bank. Seen that happen and no, it wasn't me... BTW, note that the VCC pin is +5V. With that, I'd be a little more careful than regular +3.3V.
  12. xc6lx45

    Vivado License on Cmod A7: Breadboardable Artix-7 FPGA Module

    If you have doubts about your current license, it might be the easiest route to simply build a test design and see what happens. Personally, I suspect that tool vendors make a great deal of money from uneducated users and are reluctant to change that. This as constraint file set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports CLK12] set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {LED}] and module top(input wire CLK12, output reg LED); always @(posedge CLK12) LED <= LED + 1'b1; endmodule should do the trick. Choose xc7a35tcpg236-1 under Vivado "project settings".
  13. xc6lx45

    XADC conversion rate

    I think the ADC requires 26 cycles per conversion, kind of an odd number. If you feed it an input clock of 104 MHz, it will give exactly 1 MSPS (according to my XADC wizard on Artix 7) with an internal clock divider of 4 (26*4=104). BTW, your register printout seems to show a clock divider of 25 (0x19?? in register 42), so I guess this will run much slower?
  14. xc6lx45

    Driving DAC cs4344

    BTW, thinking back to when I wrote those comments in the code: I generate the SPI clock signal from a regular information bit. Timing analysis guarantees that the signal is stable at the edges of the clock it is associated with. It does NOT guarantee that the signal is glitch-free in-between. Glitches on a clock signal means the slave may see more than one clock edge and bits slip. Thus the comment. If it comes straight from a register, the signal will be clean. If there were combinational logic behind it, there could be glitches => avoid. It didn't give me any trouble so I guess it's OK for home audio. Please don't use in pacemakers, autonomous driving or thermonuclear missiles.
  15. xc6lx45

    Feedback on a register file design?

    Laughing out loud. I thought, gate crashing the local motorcycle club with a "Harley s*cks" T-shirt. Labor of love, that's the point. Sometimes it's just healthy if someone states the obvious. And Zynq, agree fully. But that's essentially an ASIC part on the die.
  16. xc6lx45

    Feedback on a register file design?

    Ummm. A quick reality check: So that one asks later, why did no one tell me. There is no "business case" for high-end CPUs on FPGAs. Period. Meaning, it will always be dramatically slower, more expensive, less energy-efficient than a dedicated chip. Maybe pick a Raspberry Pi as reference. Yes, as a learning experience it's a great idea - probably the best that has shown up in amateur electronics in the last decade or so - and I don't even want to rain on anybody's parade. But, a general purpose CPU on a general-purpose FPGA just won't fly, it can never be competitive against an ASIC. It's like mining bitcoins on a PC, the basic facts are against you. So just keep that in mind before heading out into a dead end. CPUs on FPGA, the journey is the destination.
  17. xc6lx45

    Driving DAC cs4344

    Hi, here is the file on google drive: https://drive.google.com/file/d/1w5bB3QoOe6YPBvX45e82ZW1CK0tdeHh4/view?usp=sharing
  18. xc6lx45

    Driving DAC cs4344

    if you find nothing better - it's a fairly popular component - I've made it work the hard way, once upon a time. See attachment. This was on a Spartan 6. CS4344_DAC_demo.zip sk61_CS4344_DAC.v
  19. xc6lx45

    Vivado License on Cmod A7: Breadboardable Artix-7 FPGA Module

    Now this doesn't exactly answer your question (sorry...), but: The free Vivado WebEdition supports the CMOD A7. I don't need any device-specific license. You want to know about non web-edition features?
  20. xc6lx45

    Debugging the DDR3 pins?

    One popular run-of-the-mill testing method is to alternatively write (and read) the alternating bit pattern 0x55 and 0xAA. "Hello bits, are you all there?"
  21. xc6lx45

    Streaming FFT data

    Maybe this is off-topic. But: note that if you only need one (or a few) bins of the FT, you can calculate each at one multiplication per streaming sample using the so-called "Goertzel" algorithm. See http://en.dsplib.org/content/goertzel/goertzel.html (16-18) for an example. This might simplify the system design somewhat...
  22. xc6lx45

    Feedback on a register file design?

    Not saying I would have thought of it (but then I don't design compilers & CPUs). It might be just the following code: int* a = (something); int b = *a; // and from now on, a is never used again The lifetime of b begins when a ends, so a and b get optimized into the same register.
  23. xc6lx45

    JTAG-USB Question

    ... and FYI: xc3sprog can be modded trivially if you add the IDCODE for Artix and the JEDEC ID of the EEPROM (no guarantees on the latter, but worked for me once, with the above board).
  24. xc6lx45

    JTAG-USB Question

    Hint: You can buy an officially licensed adapter module here: https://shop.trenz-electronic.de/de/TE0790-02-XMOD-FTDI-JTAG-Adapter-Xilinx-kompatibel The description is awfully German :-) but it's pretty straightforward together with a TE0725 board (which is BTW interesting in a sense that it's available up to Artix 100 size and EOL predicted ~2028) Caveats: Weak regulator (Clearly stated in the doc, but in my experience a Microblaze test design will run on USB bus power) Does not support 30 MHz signals, if you intend to do your own MPSSE JTAG programming. Clock divider 1 / 15 MHz works reliably.
  25. xc6lx45

    Feedback on a register file design?

    >> a general purpose CPU CurtP, you could have a look at J1: http://www.excamera.com/files/j1demo/verilog/j1.v It's a beautiful design. Not that I'd propose Forth for any real-world work but it's perfect for a simple hardware implementation. It might even make make "business sense" in Picoblaze territory. There is a VHDL port, too, but possibly not as concise.