xc6lx45

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Everything posted by xc6lx45

  1. Hi, just an observation: In the last screenshot, the message box reads "USB: 5.09 V 1058 mA". Isn't the USB 2.0 limit 500 mA? Seems a bit high...
  2. xc6lx45

    Basys2

    Most likely it's US export restrictions then. A topic where I'd tread really carefully. Or the next US trip gets an unplanned extension, food and shelter courtesy of the US government...
  3. xc6lx45

    Basys2

    Hi, Basys3 is Xilinx Artix-7 FPGA (XC7A35T-1CPG236C) . I believe it's the same as e.g. on the CMOD A7, which works with the free (webEditition) Xilinx license. The Basys2 page states The Basys 2 board works seamlessly with all versions of the Xilinx ISE® tools, including the free WebPACK™ In my understanding, you shouldn't need a paid license for either board. They may have shipped one for additional features (e.g. Microblaze and on-chip scope in ISE) but they aren't mandatory to work with the board. Try to generate a free ("WebEdition") license for Vivado (Basys3 board) and ISE (Basys2). Note, you may need to download an ISE version earlier than 14.7, according to the Xilinx download page. This is the link from Vivado license manager: And ISE. In the main window, they appear in the "Help" menu.
  4. My understanding is that the license file is simply read by the software, and there is nothing else going on behind the scenes. If you'd uninstall and reinstall the same version, you'd be back where you started. This, however, is just an end user's view. If it means anything, my own .lic file is from 2014, and has served me through several Vivado (and most likely ISE) versions. Just a random thought: If you need to worry about 24 gigs of HD space, you may be facing an uphill battle in FPGA territory... People do custom builds with water cooling, overclocked quad-channel RAM, high-end SSD drives, and still it's too slow (and HD performance goes south unless there is plenty of empty space).
  5. Hi, as far as I know you can install and keep multiple versions independently on the same PC, on the same license file. Xilinx groups them in the start menu by version number, that's no coincidence.
  6. >> vivado15.1 Are you sure? This is my "Help/About Vivado" dialog of the latest free "webedition", which works for me without flaw for the CMOD A7: If really "15" it sounds like a fairly old version.
  7. Hmmm looks like I've exhausted my upload quota for today... 0v5 link on google drive: https://drive.google.com/file/d/1PfloGnO0D80ZMiJ5eGi0AKRI1IgXWe9s/view?usp=sharing
  8. Hi, in Bogdan's code example, the "if..." clause runs once every (e.g.) 12 000 000 cycles. The "else..." clause runs 11 999 999 times out of 12 000 000. I think you're toggling the LED at a speed much faster than the human eye can follow, but effectively it's only on one half of the time, so it looks less bright. If you allow me an opinion: Learn to use a simulator. "iverilog" is great, with "gtkwave". It takes an hour or two to get started, but you'll earn this time back within a day. It brings the bugs out in the light, with no place to hide (... warning: the baddest bugs don't fear the light... story for another day ) And, more opinion: the first steps on the FPGA learning curve are near-vertical (new language, so many tools) but it flattens out eventually. A guaranteed (but slow) way to get up: every time you don't understand something, dig down to the bottom unless it's obviously clear; don't leave any loose ends behind.
  9. === LabToy 0v5 === Voltmeter rewrite, additional readouts Main page buttons raise sub-windows Actually quite a bit has happened under the hood. The internal architecture now supports feeding any number of sinks from a FIFO data stream (the ADC connects to both the voltmeter and the file writer). On the surface, only the voltmeter changes. Please note the tooltips! It now implements true moving-average statistics over a 200 ms window. This particular length suppresses both 50 Hz and 60 Hz power line hum, and responds still near-instantaneously. The screen refresh rate is actually higher than the window length, the two are independent. New readouts for: VMax: Highest sampled voltage in the last 200 ms window time interval VMin: Lowest sampled voltage in the last 200 ms window time interval VRMS: "True RMS DC average" over the window (put this number into Ohm's law and it will give the correct power dissipation over some resistor) VRMS, AC: "True RMS AC average" over the window (put this number into Ohm's law and it will give the correct power dissipation over some resistor that is AC-coupled e.g. using a sufficiently large capacitor or transformer) The latter two should give similar readings to an "expensive" (true RMS) multimeter. Speaking of "expensive", on my board the readings are about 10 % off... Until now, the results are calculated rigidly based on component values taken from the schematic, with no regard to tolerances. Maybe it's time for some calibration algorithm, stay tuned... The following are drafts for a future online help for the voltmeter. It's first-semester stuff. Hope I got my equations right Well I guess it's one of those exams few people want to face a 2nd time... PS: For best results with the voltmeter, set a high ADC sample rate e.g. 720000 in the "capture" window. CPU load goes up, but so does bandwidth.
  10. Hi, it may be a good idea to not make that information public (in other words, delete the screenshot and send it as a private mail). This might complicate matters if you're trying to re-claim a license. Just my $0.02.
  11. Hi, did you build the bitstream for the correct device?
  12. === 0v4 released === Voltmeter: Option to extend the ADC input voltage range (and raise the probe impedance) by using series resistors Voltmeter scaling slightly tweaked (fullscale changed from 3.3 V to 3.32 V calculated from the schematic) Added Octave function to load binary ADC data to the installer On my board, there is a ~50 mV offset to both ADCs. in other words, leaving the input open shows 50 mV. I may add some calibration in the future to get rid of it. EDIT: Attachment deleted because of quota. Please pick a later version, there are no known downsides
  13. Thanks for the measurement. Please note: You're showing the PWM digital bitstream with an almost sufficiently fast scope. Obviously it's a sequence of 0 and 1. And I replied to this already once before: Here is the 10 kHz waveform, using the built-in XADC with ~1 MHz bandwidth. Anybody can repeat this without additional hardware. And the same on my favorite electronics pocketknife (which is BTW the inspiration for labToy): If there is any confusion on the topic, please refer to Xilinx application note 154. There is a detailed analysis on filtering. For "typical household use", it may work well enough without explicit filtering . E.g. the built-in XADC or a LM741 opamp in a typical breadboard circuit have an inherent bandwidth of about 1 MHz, which will do the job. Now regarding the square wave measurement: You're showing the "Square 01" signal, which involves PWM => filtering discussion as above. Now there are two options in the waveforms menu: "Square 01" is an analog signal and allows level control. This shows the PWM bitstream on a fast scope. "LOGIC 10" is a digital signal and shows cleanly on any scope. But, it's always digital fullscale (no PWM), therefore the level controls are grayed out. The "01" or "01" denotes the phase relative to the generator's sync signal that can be logged in the logic analyzer.
  14. === 0v3 released === export binary ADC data tweak to sinc8 multitone waveform (8th harmonic was slightly off) === DAC performance === Here is some experimental data. It's completely taken with "on-board tools" using the XADC, no external filtering. Anybody can repeat the experiment with a patch cable. The test signal is a sine wave at 1 kHz (use vMin = 0.1 V and vMax = 3.2 V, leaving 0.1 V headroom on either side). It's the "X" on the left. The fuzzy stuff on the right are harmonics and spurious products but they are about 60 dB down (1 millionth of the signal energy each). There are about three dozen of them => the signal is fairly clean. At the bottom we see the noise floor, well below the -80 dB line (I may not directly compare noise and signal levels from the plot, but I can compare two plots). The spurs at 180k and 360 k are caused by the noise shaping of the DAC. Zooming in on the signal: The 4th harmonic sticks out at -57 dBc (distortion: 1/500000 of the signal), otherwise they are at or below -60 dBc === Frequency response === There is a built-in multitone test signal (sinc8) with 8 harmonics. This is the measured result for 10 kHz fundamental frequency. Harmonics largely below -40 dBc. Zooming in on the passband, there is 2 dB amplitude drop at 80 kHz. Is this the DAC or the ADC? A question for another day... it actually works much better than my expectations. Finally, a note on the "noise shaping": First, any DAC requires a reconstruction filter (lowpass). This one is no exception. See Wikipedia. A "noise shaping" DAC moves noise to higher frequencies so that it can be filtered away easier (the higher the better) and does not impair the frequency band of interest. This is the measured performance when I disable the "noise shaping". Comparing with the first picture, the noise floor is about 17 dB up. In absolute terms, noise shaping gets rid of 95 % (=17 dB) of the unavoidable noise and moves it to higher frequencies. Works as designed. === Attached === The latest release (the DAC is the same BTW), and an Octave script to generate the above plots from captured data. Happy hacking (and beware of the +5 V pin...)! dacCheck.m labToy0v3_beta.exe
  15. Hi, I don't own the same device. That said... >> It could be the AD2 was starting to fail ...I'd get another USB cable before anything else... they fail often. You could have a look into the device manager (press Windows key and X, click on the "Device manager" menu entry). First, when you plug and re-plug the cable, the list should be refreshed and flicker (99 % certain this is the case, otherwise the cable is totally broken) Now comes some detective work, try to locate the device. If in doubt, pull the cable and it should disappear. Maybe (!) you have to manually uninstall the old driver (right-click, uninstall device) when it competes with the new one. And sometimes the "properties" dialog has meaningful info what went wrong PS if you have the option of rolling back to Windows 7, you might reconsider... MS systematically cuts away functionality a developer needs, e.g. every failed assertion in my code "looks for a solution" and sends a bug report to MS and there seems to be nothing we can do about this.
  16. "Pocket knives" have no business in any commercial kitchen. They don't meet basic hygiene standards, pose an increased risk of injury and aren't particularly good at anything. Still people happily use them to slice pizza.
  17. There is no way to filter the noise digitally. Only move it where filtering is most convenient. But you need an analog filter in any case, or just live with it. It's a pocket knife, remember. Feel free to use it in creative ways. If RF noise is a problem for you (and it won't be for most people), just add adequate filtering. A parallel capacitor and / or a simple RF choke will work wonders.
  18. There's no drama involved. There exists an official Xilinx application note for (I think) a first order sigma-delta converter that does just the same. There's also no shortage of designs that use this approach (e.g. this one). And generating an analog signal with a digital output is the standard approach nowadays for audio, used in just about any CD player, iPod etc within the last 20 years or so.
  19. BTW here's one more C "gotcha". Probably not the problem here but worth mentioning. This #define CLOCKS_PER_SECO TIMER_FREQ_HZ is going to bite you when a sloppily written header says #define TIMER_FREQ_HZ something-1 Use #define CLOCKS_PER_SECO (TIMER_FREQ_HZ) instead.
  20. Hi, I suspect the problem will disappear if you create a "double" variable for everything you want to print, and avoid expressions as "printf" arguments. C's automatic type conversion rules are a trap for the unwary, they got rid of it completely when they designed C#. printf is special (same with some other "functions" e.g. min() that are usually macros) because the type of the arguments isn't fixed, as in a common function call. Example (this particular line seems to work, it just shows the idea). myTotalTime = ((double)(end-begin))/(double)CLOCKS_PER_SECO; The constant "2" is suspicious. It might cause the return expression to be standard int. "2UL" should do, or ((uint64_t) 2)
  21. OK, I recompiled it, shouldn't require 64-bit now. Attached. There is a tooltip for the generator output pin and its location if I hover over the checkbox to enable the generator. More documentation, maybe later. Rome wasn't built in a day. Now the DACs: You may be surprised but it was designed in on purpose (not as a FM radio jammer). The keyword is "noise shaping". With single-bit outputs I have no other option than PWM (one-bit quantization). That's incredibly noisy and there's nothing I can do about the total noise. What I can do is move most of it to higher frequencies. A sigma-delta converter would do that smoothly but there are reasons why they don't work too well in this application (rail-to-rail output, idle tones for DC-ish signals). I'm clocking the DACs at 250 MHz, with a four-bit deterministic PWM reference and the other bits pseudorandom => noise spikes at n*15.6 MHz. I guess you're listening to the 6th harmonic of 250/16 MHz. Have to admit I didn't even simulate this. Just tried in hardware, and it worked well enough (the sigma-deltas didn't). The "take-no-prisoners" approach to output drivers (LVTTL, 24 mA, fast slew rate) might also play a role in its efficiency as interference generator... I might take the thing to the shielded room at work just for laughs. Hope the radiated emissions don't burn the expensive EMI scanner... If in doubt, use a capacitor to ground as lowpass filter. The PMOD outputs already provide the series resistor. BTW, the purpose is a "swiss army knife" style electronics application. It'll generate a test tone for a guitar amp, measure what happens to the bias voltages (use appropriate series resistors with the ADC..) and even spit out 440.0 Hz to tune the guitar. It's not meant to self test or "demo" the FPGA / board, that's out of scope. labToy0v2_MSIL_beta.exe
  22. Agree... maybe I'll remove the jitter filter to improve the carbon footprint...
  23. Oh that's easy to fix. Just put it into a temperature-stabilized oven :-)
  24. OK I think I understand the point. It's mainly a testcase for my own framework, has evolved some life of its own... OK sometimes it just feels good to do something useful (well, potentially hypothetically useful or whatever as long as it's not powerpoint slides...) The GUI stuff is the fun part, but the real work is in the FTDI-MPSSE USB engine beneath, 125 us round-trip time... I can turn that into a DLL or an application-specific command line utility within a couple of minutes, with any number of independent FIFOs to custom RTL via copy-and-paste.