xc6lx45

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Everything posted by xc6lx45

  1. xc6lx45

    custom FTDI JTAG

    If you read through the forums, you'll notice more than once that the Digilent programming circuit is considered "proprietary" (even though it contains an FTDI chip). Here is an example that the technology is licensed (3rd party Digilent-compatible JTAG vs the same hardware without license). I don't work for any of the mentioned companies but I'd guess your answer will be "no".
  2. Hi, an implemented passive adaptation can be found on Trenz' ZynqBerry: https://wiki.trenz-electronic.de/display/PD/TE0726+TRM#TE0726TRM-CameraSerialInterface(CSI-2) (see R48 / R49 in the schematic). Just for the record, this was what I had in the back of my head with the idea of "slapping two boards together". Again, if you intend to build this from scratch without high-speed scope and lots of time, this does look like a high-risk project...
  3. Don't get this wrong but something about your questions tells me this is a "high-risk" project... Have you thought about getting two identical boards with a tested-and-tried camera interface with working drivers, and simply slapping them together with a ribbon cable e.g. 32 bits wide at 100-ish MHz clock frequency?
  4. Hi, I'm sure there will be some long follow-up answers. I specialize in short answers, so here we go 🙂 Engineers are frighteningly unsystematic. What engineers are good at is cutting corners. Either you're completely in over your head, or you are facing an easy problem. For easy problems, engineers do a quick sketch on a paper napkin (skip if no napkin is available) and start coding. So what you need is the Verilog skills to write down a FSM. Essentially, it might look like this reg [7:0] state = 8'd0 always @(posedge clk) begin switch (state) case 8'd0: if (something) then begin ... state <= 8'd1; end case 8'd1: if (something) then begin ... state <= 8'd2; end endcase // this must be at the bottom of the enclosing begin...end block if (synchronousReset) begin state <= 8'd0; ... set everything else to init values end end It might look completely different (matter of style) but avoid e.g. asynchronous reset as commonly found in pre-FPGA tutorials. Then write down what you think it should do. Simulate. Figure out why it does something else. Rinse and repeat and also update your understanding of what you think it should do... Oops. It wasn't that short.
  5. xc6lx45

    Verilog Question

    >> Therefore it's 2^3 and can address up to 8 bits not bits but the value goes 0..7. The original design needs a value of 6 so 3 bits is the minimum. Makes sense. There is an implicit division-by-two in the negation of the output flipflop clk_track <= ~clk_track; so you need to set half the division ratio. That said, DO NOT use this approach for creating an actual FPGA clock. Modern FPGAs are more complex and distinguish between dedicated "clock" signals and "information signals", with distinct routing resources. The clock divider would create a bridge from an information routing resource to a clock routing resource, and that gives you a warning in Verilog and a sub-optimal design.
  6. Hi, I think your question until now is completely independent of the GSM module, but it's about the UART. To debug that, put the GSM module aside for now and simply connect the Tx- and Rx pins on the zedboard side (loopback test).You should be able to read back the same data you're writing.
  7. Hi, are you aware that the chip has only two physical AD converters, plus analog multiplexers to feed them from a larger number of inputs? This is where the sequencer comes in.
  8. Hi, the above-mentioned "clocking wizard" is your interface to a hardware unit on the FPGA called "clock management tile" (CMT) (see here page 13). The functionality is not easily modeled in "vanilla" Verilog, it's based on analog / mixed signal circuitry on the chip. What you can do is instantiate one unit (via the "clocking wizard") and use the Xilinx-provided model, ideally in the simulator Vivado provides. When this is working, you'll feed in a 12 MHz clock at the input and get an 8 MHz clock at the output. At some point you'll run into the problem that the minimum output frequency of said hardware unit is 4.688 MHz, it won't give you 1 MHz. That's where my previous post starts: Use the CMT to go from 12 MHz to 8 MHz (CMT / MMCM-internally: by going from 12 MHz to 768 MHz = multiply by 64, then down to 8 = divide by 96). My post gives you the missing division by 8. And again, the disclaimer, this is not a standard design procedure for reasons I won't go into. It'll get us from A to B but we're driving on the wrong side of the road...
  9. xc6lx45

    spi zynq

    I don't think there is a single definite answer but to give you some number, I've once used 60 MHz between an Artix (~Zynq) and a Raspberry Pi.
  10. I guess the question was already answered...anyway, here's a quick example that works correctly in Vivado, within a module...endmodule context: genvar j; generate for (j = 2; j <= NWRDELAY; j = j + 1) begin always @(posedge i_clk) begin wa[j] <= wa[j-1]; wd[j] <= wd[j-1]; we[j] <= we[j-1]; end end endgenerate
  11. Hi, If you're using the 12 MHz clock, it won't be a high-performance design anyway, no point in analyzing "below the noise floor". Just keep in mind that the general problem might be more complex than this simple solution. Anyway, If I needed this 1 MHz clock generator myself in the lab and quickly, I'd use the clocking wizard to 8 MHz output freq. Then... reg [1:0] counter = 2'd0; (*DONT_TOUCH="TRUE")reg tmp = 1'b0; (*DONT_TOUCH="TRUE")reg theOutputReg = 1'b0; always @(posedge clk8M) begin counter <= counter + 2'd1; if (counter == 2'd3) tmp <= ~tmp; theOutputReg <= tmp; end This should be still better than (don't use this) wire theOutput = (counter >= 3'd4); // with a 3-bit counter
  12. Hi, for LEDs, you MUST add resistors, otherwise they'll blow. For example, for a red LED assume a fixed voltage drop of 1.2 V. For 6 mA, use (3.3 - 1.2) / 0.006 V/A = 350 ohms. You do not need to use an external decoder when your FPGA has enough IOs. You paid for the FPGA, why not use it.
  13. The Wikipedia article ends with ... may be liable to a fine and, in some circumstances, imprisonment. No but they'll send you to jail for that 🙂 Seriously, spend some time on the topic. You don't get a CE stamp by having a CE stamped component in your product. It just doesn't work like that.
  14. They are very robust. Xilinx is a bit shy in telling numbers, but their posts indicate that they are short circuit proof. https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Effect-of-short-circuit-on-V6-outputs/m-p/227493#M13565 https://www.xilinx.com/support/answers/23277.html I got the impression that reports of failed voltage regulators are more common than busted FPGAs (expect that blowing one pin kills the whole IO bank).
  15. xc6lx45

    FPGA projects

    Blinking a LED and UARTs is an excellent plan to start. You can spend months with those and learn efficiently. And yes, spend the time with simulation, use hardware mainly as reality check and for motivation. I'd go for iverilog & gtkWave first. If both are power tools, iverilog comes "batteries included", Verilator requires a 3-phase outlet 🙂 Edit OP asked for VHDL. Never mind... maybe the built-in simulator is sufficient.
  16. Well, I think the OP had explicitly ruled out JTAG, otherwise xc3sprog can do the job (just add the IDCODE, the last time I checked this was the only change necessary for Artix). Or am I missing something here?
  17. unsolder flash / program flash / resolder flash 🙂 OK most likely that's not what you wanted to hear. .. The men in white coats might have some ideas (e.g. needle-probing a Flash in a large-pitch package isn't that hard, and / or lift off the MISO pin with a scalpel and connect your own Flash). Other than that, I think you've ruled out the possibilities (001 is "Master SPI", table 2-1). How would you think does the manufacturer of the board handle this?
  18. BTW, the terminology isn't rigidly defined, but usually the time line goes - engineering samples"ES" - customer samples "CS" - volume production Those are important milestones in a typical ASIC design process. The ES may be needed for example internally for test "engineering" to bring up the volume test. "C"ES sounds to me like Xilinx is handing out early silicon (therefore "engineering" in the name) to some customers, with a disclaimer that some features are still broken. Makes perfect sense and it seems highly unlikely that those would ever be sold to us end customers, who are left scratching their heads at said disclaimer...
  19. No, "production" silicon is what is sold through regular channels. "Engineering samples" are given out to (large) customers before a device goes into production but you wouldn't be able to get them as an end customer (it's a contract question but most likely, the resulting devices would be forbidden to be sold commercially)
  20. Now actually I think there are more than two pins on the CMOD A7 that support ADC (besides the two I mentioned earlier. Those have external resistors, but I can add them also externally to the module or use other analog circuitry) See block IC2D on the schematic, sheet # 3. https://reference.digilentinc.com/_media/reference/programmable-logic/cmod-a7/cmod_a7_sch.pdf The interesting signals have _ADxyP and _ADxyN in the pad name on the FPGA. Those can be used for XADC.
  21. I think 47565 applies only to engineering samples (ES), not to production devices. >> 'na' means the issue does not apply. Production: na "CES" is used at least by NXP meaning "customer" engineering samples. Probably the same for Xilinx.
  22. xc6lx45

    CLK not lvcmos18

    Any drive strength (just pretend the option does not exist). It's not sensitive, more related to the slew rate than the level. Unless you know otherwise, it's unlikely to fix your problems... One example where you'd reduce drive strength is to limit emissions and coupling, use the slowest possible signals that get the job done. Your signal looks clean, the edges are pixel-perfect. I'd look at the scope, not the FPGA.
  23. Hi, look at the board schematic and check, which ADC capable pins are routed out of the board. For CMOD A7, the answer is simple: There are two, and each is single-ended with a resistive divider that accepts 0..3.3 V input voltage for fullscale. Those can be mapped to ADC 1 and 2, and sample synchronously. This is the authoritative reference, double-check your expectations on what can be "configured" (it's very limited compared to other functional units since it's analog): https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
  24. xc6lx45

    CLK not lvcmos18

    Hi, FYI: you couldn't change the output drive voltage through programming. It's set by the bank's supply pin. Is your scope loading the signal with 50 ohms - there's a "50 ohms" icon on the screen - and / or did you configure the scope impedance correctly for your probe? You observed that it depends on drive strength, so it looks like you're accidentally loading the FPGA output...
  25. >> what I need considering what ADC circuitry I use. BTW 7-series (Artix) and Zynq have built-in dual ADCs, 1 MSPS, 12 bit specified but more hardware bits, up to 16 inputs that may or may not be routed out of the board (e.g. CMOD A7 brings out only two, but it's a start). The XADC is not a trivial piece of equipment e.g. several modes but fairly accessible once you have it working.