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Everything posted by xc6lx45

  1. Hi, as I may not have time for FPGA work for a while - just started in a fascinating new role related to high-speed digital diaper changing - I decided to post this now. Here's the Github repo (MIT-licensed) The project provides a very fast (compared to UART) interface via the ubiquitous FTDI chip to a Xilinx FPGA via JTAG. Most importantly, it achieves 125 us response time (roundtrip latency), which is e.g. 20..1000x faster than a USB sound card. It also reaches significantly higher throughput than a UART, since it is based on the MPSSE mode of the FTDI chip. Finally, it comes with a built-in bitstream uploader, which may be useful on its own. I implemented only the JTAG state transitions that I need but in principle this can be easily copy-/pasted for custom JTAG interfacing. So what do you get: On the software side an API (C#) that bundles transactions, e.g. scattered reads and writes, executes them in bulk and returns readback data On the RTL side a very basic 32 bit bus-style interface that outputs the write data and accepts readback data, which must be provided in time. See the caveats. In general, a significant increase in complexity over a UART. The performance comes at a price. In other words, if a UART will do the job for you, DO NOT use this project. For more info, please see the repo's readme file. For CMOD A7-35, it should build right out-of-the-box. For smaller FPGAs, comment out the block ram and memory test routines, or reduce the memory size in top.v and Program.cs. I hope this is useful. When I talked to the FTDI guys at Electronica last week I did not get the impression that USB 3.0 will make FT2232H obsolete any time soon for FPGA: They have newer chips and modules but it didn't seem nearly as convenient, e.g. the modules are large and require high density connectors. In FPGA-land, I think USB 2.0 is going to stay... Cheers Markus
  2. xc6lx45

    Cmod S6 - Multilayer?

    You might go to Texas Instruments' site (or AD or both) and find documentation for some $500 high frequency ADC or DAC eval board as example to study.. There's nothing wrong with copper planes, generally. Free-standing structures (such as non-connected filler polygons) can be bad, if they resonate. So are loops if the driving wire spans an area together with the GND return wire (for which the ground plane is an obvious solution). The worst resonators have high quality factor meaning loose coupling meaning it can be surprising how the energy managed to couple in. There's no such thing as too many ground vias... Note, your ground plane can do very interesting things in combination with the metal box it's in (resonant cavity) but that's a different story.
  3. xc6lx45

    busbridge3: High-speed FTDI/FPGA interface

    laughing out loud ... Formula-1-performance is niche business, combine harvesters bring home the money, walking barefoot is the norm. And why not, I'm even discouraging people to touch it as long as a UART does the job. Same as with fast cars, speed is largely overrated. Those who know otherwise, you know who you are 🙂
  4. xc6lx45

    Implementation Strategies

    >> Is there a strategy that targets the re-use of logic? this is a slightly different question, but can help the tools with timing: Sometimes I need to replicate logic that starts with an input register on the same data for all instances (e.g. multiple blocks using identical high-frequency counters as internal timebase). The tools will recognize them as logically equivalent and try to use one shared register. This is bad, when the downstream logic is timing-critical. In this case, I can manually flag the register as "DONT'T TOUCH" so the replicas are preserved and placed closer to the critical logic. Optimization would eventually reach the same conclusion after thinking long and hard. There is a "-keep-equivalent-registers" option that makes this the default. The "rebalancing" option is under Synthesis options "-retiming".
  5. is this the absolute group delay or the delay uncertainty? The latter you can calibrate out. And I can interpolate mathematically between samples in a way that is indistinguishable from a faster converter, for a bandlimited signal. Absolute latency, yes, the sample rate sets an obvious limit, but read the converter datasheet carefully (internal processing latency). Now I'm guessing on what you're trying to achieve: note that sampling rate has nothing to do at all with time-of-arrival estimation error (theoretical limit: the so-called "Cramér-Rao" bound. It depends solely on the spectral shape and some signal-to-noise ratio).
  6. xc6lx45

    Implementation Strategies

    Hi, it may help to close timing. But most likely it's a dead end, for several reasons: P&R is at the end of the design process. It fails here but the root cause lies somewhere else most likely (blind guess, assuming from the nature of the question that you're not a power user), the problem lies in the constraints. Specifically, a missing "false_path" to timing-uncritical IOs like switches or LEDs. This can be a timing killer, because it leads to an impossible job for the tool. inserting pipeline registers will most likely fix it. In most cases (no closed loops, no rigid latency constraints) it's fairly easy to insert single-cycle delays across a "cut plane" through the design, leaving the functionality unchanged. Regardless of the strategy, check that "register rebalancing" option is enabled even if you manage to close timing once by tool options, the design will be difficult to work with, long P&R times and no guarantee of success. When squeezing a commercial, large volume design into the smallest possible device this may be worth the trouble, but not during R&D unless the design is "pushing the envelope".
  7. xc6lx45

    QSPI Program Load is Slow

    Hi, I suspect you're using slow default options for bitstream generation. Increase the clock rate and enable bitstream compression. It should be much faster.
  8. xc6lx45

    Continuous collection of photodiode data in LV

    BTW, if you use a 1 MSPS ADC for 10 kHz bandwidth, you may gain the two bits from oversampling gain. E.g. accumulate 64 samples and use sum[21:6]. It causes some deviation in the frequency response "sin(x)/x", if in doubt use less averaging than theoretically possible. Just be aware that the smooth early learning curve is designed carefully into some technologies e.g. Labview. FPGA in general is not one of them... No free lunch here. I'm still hoping someone will say it's possible with AD2.
  9. xc6lx45

    Arty A7 -35T gets hot, even when unprogrammed

    as a general comment, it's fairly common to have unplaced components on a PCB, especially a sparse one where there is no pressure to reduce size. Your readings are all over the place - I doubt that with 12 V (0.12 V?) on the 5V net and 3.3 being the new 1.8 (C181) there would be any magic smoke left inside the board... But with a proper multimeter (make sure you have a good connection to GND on the black lead), I see a good chance that you'll be able to spot the problem, basically if any net is significantly off its designated value.
  10. xc6lx45

    add on for custom designed system

    An MBED LPC1768 might work. You need to connect Ethernet magnetics, but that's more a mechanical issue (flying wires worked for me). The C code below reads a file "config.txt" from the MBED's USB drive, which is a simple way to set the IP address by editing the file in notepad.exe. char buffer[256]; char ipAddress[256]; char subnetMask[256]; sprintf(ipAddress, "%s", ""); sprintf(subnetMask, "%s", ""); int port = 7; FILE* f = fopen("/local/config.txt", "r"); if (f != NULL){ int n = fscanf(f, "%s", ipAddress); if (n <= 0) goto endOfFile; n = fscanf(f, "%s", subnetMask); if (n <= 0) goto endOfFile; n = fscanf(f, "%s", buffer); if (n <= 0) goto endOfFile; port = atoi(buffer); endOfFile: fclose(f); } EthernetInterface eth; eth.init(ipAddress, subnetMask, ""); eth.connect(); printf("IP address: %s (configured: %s) port %i\r\n", eth.getIPAddress(), ipAddress, port); TCPSocketServer server; server.bind(port); server.listen(); while (true) { printf("\nWait for new connection...\n"); TCPSocketConnection client; server.accept(client); client.set_blocking(true, 0); printf("Connection from: %s\n", client.get_address()); client.send_all(">\r\n", 3); // === main loop === while (true) { // === read data from socket === int n = client.receive(buffer, sizeof(buffer)); // === detect connection break === if (n < 0) goto conn_exit; // maximum length of a single reply. Anything longer will be split. #define MAX_PACKETLEN (1024) // maximum length of a single message to guarantee there is enough output buffer #define MAX_MSGLEN (16) char bufOut[MAX_PACKETLEN]; // === iterate over input characters === int ix; for (ix = 0; ix < n; ++ix){ ... work on buffer contents ... send reply: client.send_all(bufOut, nInBuf); } // for input character } // while connection conn_exit: client.close(); } it needs this ethernet library (there may be several) /* EthernetInterface.h */ /* Copyright (C) 2012 mbed.org, MIT License
  11. >> problem with the clock BTW, UARTs are pretty robust towards frequency error because the sampling instant re-syncs every byte. Electrical interference could be an issue, since there is more noise on the power supplies when the CPU is busy. What I'd try is look at the signal with a scope, or add some resistor to ground. A ferrite choke might also help, if it's a noise problem.
  12. xc6lx45

    Continuous collection of photodiode data in LV

    A couple of thoughts: What you're looking for is "streaming" data acquisition. It's fairly routine with industrial test equipment e.g. PXI or PCI based "digitizers". But, not sure what to expect with "budget-friendly" equipment. Disclaimer: I don't know the AD2 at all. You may be able to solve this problem with a $70 Artix- or Spartan FPGA module and the onboard 1 MSPS/12 bit ADC. The necessary RTL design is relatively straightforward: boilerplate XADC and dump the ADC frame to a UART on end-of-conversion. The UART data rate can go up to about 3 MSPS using FTDI's driver API on the PC side (DLL?) so e.g. 8 bit at 250 ksps should work. I think I tested 6 MBaud once but don't take my word for it and beware of "relatively" straightforward things in FPGA land... Would a 192ksps sound card work?
  13. >> but through the pins when running normally could it be a simple grounding issue?
  14. this type of board has been a staple in DIY for many decades. I doubt you'll find it documented anywhere, since it's pretty self-explanatory once you get your hands on it. Maybe this helps: Groups of five pins ("A B C D E") belong to one clip and are connected. The exception are along the red and blue lines. Here groups of five form one long busbar with 50 pins. Pin spacing is 1/10 inch = 2.54 mm If you put a small DIL IC into the center (over the depression), four holes remain for each pin.
  15. Just thinking aloud... 2 MSPS for a 10 kHz signal seems unusual. E.g. CD audio uses 0.044 MSPS for 15 kHz BW. Have you double-checked why e.g. a conventional audio codec would be insufficient?
  16. xc6lx45

    Arty A7 -35T gets hot, even when unprogrammed

    it's possible that your multimeter is in AC mode (need DC). Also double-check that the "plus" probe is not accidentally plugged in for ampere measurement (separate socket on most models) otherwise it's a short circuit. Usually you connect the minus lead to GND permanently - the interesting caps have GND on one end. Be aware that probing "accidents" (short circuits) can damage a board.
  17. xc6lx45

    Arty A7 -35T gets hot, even when unprogrammed

    Hi, just as a reality check, an unprogrammed Artix FPGA does not run hot. It's marketed as "lowest power and cost at 28 nm", this would turn back time a decade. My first impression is there is something wrong with your board (not necessarily the FPGA, those tend to be very robust). If you have a multimeter, you could check the voltage regulators by locating a capacitor on the net from the schematic. This is where I'd start looking for a hardware fault. Now, statistically speaking, most suspected board failures have a completely different root cause, so I wouldn't be surprised if this turns out to be the case. Remove all other connections. Then, the USB cable is a main suspect.
  18. xc6lx45

    XADC Simultaneous Sampling, synchronous at 1MSps

    I read it the same. I've used simultaneous sampling on CMOD A7 but this uses ch 4+12, which is a valid combination. But, I think you can get an equivalent result in "event driven sampling mode" with an external counter for CONVST, or if I'm lazy, an unused MMCM output at 1 MHz into CONVSTCLK. Disclaimer: to be confirmed in the lab.
  19. xc6lx45

    How to generate another, faster clock (CMOD S7) ?

    I think you can also copy the code from the wizard-generated output file. There may be a project option for the language of generated "output products", check that if you want Verilog and get only VHDL.
  20. xc6lx45

    How to generate another, faster clock (CMOD S7) ?

    Hi, usually I'm with you on avoiding "wizardry" but there is a risk that you're venturing out into uncharted waters. It's not a trivial subsystem, at least read the manual for the block - just kiddin' it's 114 pages Or not. Maybe check page 77, the paragraph at the bottom. Myself, I would still use the wizard, if only for the jitter estimate (it can vary greatly, depending on settings). Also consider LOW instead of OPTIMiZED for improved input jitter rejection, as long as the generated clock phase relative to the input clock does not matter. And it may help a little to cascade two stages, especially if the clock is meant for something else than driving digital logic.
  21. xc6lx45

    How to generate another, faster clock (CMOD S7) ?

    Hi, it's not handled through the constraints file. This would tell Vivado that you already have a faster clock and feed it into the chip. What you should look at is the "clocking wizard". On Vivado main screen, locate "Flow manager" / "PROJECT MANAGER" (left side of screen) There is an entry "IP catalog". Click it. Look under "FPGA features and design" for "clocking wizard". Double-click it and a GUI opens. In "clocking options", set "MMCM" (PLL won't work from 12 MHz input clock). Change "input frequency" from 100 to 12 (MHz). Under "output clock", enter your desired clock frequency. For a start, you don't need any other ports than "input" and "output" (disable "reset" and "locked"). In your RTL code, feed this block the 12 MHz crystal clock.
  22. Just a thought: If you use a plain FT2232H (e.g. via this module) you can bit-bang one bank of 8 bits at 1 MHz (max. clock rate 500 kHz). It's relatively straightforward to program. The achievable roundtrip latency "in production" is 125 microseconds or even one third less under lab conditions (because "ping-pong-ping" can be made to fit in one USB 2.0 8 kHz microframe if the PC adds no delay).
  23. xc6lx45

    State machine vs Microblaze MCU

    Hi, I suspect the complexity is far below the break-even point where the more complex architecture pays off. Making it work may even take a comparable amount of time, but you'll have to manage a design in more dimensions (user RTL, MCU, embedded code) compared to a simple "flat" RTL design. The MCU may create several problems (e.g. need for FIFOs, clock domain crossings) that can be avoided completely with a FSM. If you haven't done this repeatedly, it may take a little time to get fluent with coding FSMs in RTL. Until then, you may find you're biased towards "traditional" procedural programming, even though a plain Verilog FSM is often more concise and intuitive (opinion). For learning, why not try both. Bringing up a quick-and-dirty functional prototype shouldn't be that much work. And check what happens to the project build time when adding the MCU. Software changes are quick, though.
  24. >> having about 60uF of ceramic decoupling goodness Maybe it's even more a question of ESR than capacitance. Ceramic if money doesn't matter (e.g. Mouser: 22 µF: €4..6). The typical solution are staggered capacitors, with a quick look at the datasheet for the self resonance frequency in the impedance curve. I do this for RF (try to get a quality short at n GHz...) but if I had to make a blind guess, I'd use two orders of magnitude, e.g. 10 µ, 100n, 1n and with a nervous glance at my Voodoo doll, 10p. The CMOD A7 is reported quite frequently (possibly because it's one of the most attractive boards) but I can tell that I've run into the same issues with FTDI's reference module for the 2232H. The chip just shuts down if it doesn't like what it sees on VCC. It took a long Friday night in the lab to prove without doubt that our system is sensitive to USB cables. We changed the design and shipped with non-detachable cable. Zero issues so far.
  25. xc6lx45


    I'm wary of Matlab magic converters. Maybe they actually work and generate results that fit into an entry-level FPGA(!). If so, I'm the wrong guy to comment. That said: If FPGA is a must, I would try to renegotiate the project scope to use a MCU (softcore or better the ARM on a Zynq board) with FPGA accelerators. Then implement the prototype in plain C. Which you can test on a standard PC. Then strip it down so it runs (very slowly) on the target platform's processor. Then create FPGA accelerators for select functions and test them independent of the algorithm. Maybe FFT is already enough (the MCU should be handle the log() with a fast approximation function). Now if I had to make a project plan for a newcomer working independently, I'd say a month, or two to be on the safe side...in reality probably three.