xc6lx45

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About xc6lx45

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    RF / DSP / algorithms / systems / implementation / characterization / high-speed PA test and creative abuse of Pedal Steel Guitars

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  1. Hint: You can also download the Zynqberry design files from git and use free Altium viewer to look inside.
  2. Hi, did you check the boot mode configuration section (QSPI vs SD)? See https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual section 2 - Is the jumper set correctly? - if QSPI, is there a valid FSBL in one board and not the other? I wouldn't be surprised if there a default FSBL in the working board that tries multiple options until it finds the first bootable image. An easy way to check is to clear the flash of the working board. If it stops working, you've found the root cause (obviously it'll "break" the working board temporarily but b
  3. If you want an opinion, tutorials aren't as helpful as you might think. They make you achieve wondrous things and give the illusion of learning. But have you really made the knowledge your own so you can apply it independently? Probably not. You may get better results following the tutorial only loosely, as a general guideline and when you get stuck (e.g. after banging your head against the problem for an hour or a day, but not after 15 seconds). Most certainly, being led by the hand won't take you anywhere near "master"... IMHO, what you absolutely should do (as you asked) is r
  4. I think the first thing I'd check is the jitter performance of the available DAC clock (its impact is proportional to the highest frequency component you're generating). The second thing I'd check is 14 bit (or whatever Nyqust equivalent performance they promise) against the LTE uplink specs. See TS 36.101. I don't think it will fly but I haven't done my homework (nor do I have the input what you're actually trying to achieve e.g. in terms of specs compliance). Check unwanted emissions, not so much close in to your signal (where the requirements are quite forgiving) but far away "out-of-band".
  5. OK I just read the LTE part. I suspect this is a RF systems design question, lacking the analog / RF upconverter (which is outside the FPGA). 30.72 MHz sample rate for LTE20 is standard at baseband. Upsampling by 8 to 245.76 MHz sounds meaningful as well (depends on the converters / filters that are available). What's missing is the step from there to RF, which might be either direct conversion (using the BB signal centered at 0 Hz) or something more complex (using a non-0 Hz DAC signal) which is easier from RF point-of-view e.g. thanks to the lower ("non-infinite") fractional bandwi
  6. A sneaky way out of it is to use n (e.g. n=8 ) generators in parallel, with a phase offset of 1/n sample. This is literally a "polyphase" approach. For high-end fast DA / AD converters you won't be able to operate at the converter's clock rate on an FPGA so it needs to be split on multiple, parallel lanes anyway.
  7. Hi, it sounds very unlikely. Now it does happen that boards fail (which is very rarely related to the FPGA itself, but more often unreliable USB cables, connectors, failing voltage regulators, PCB microcracks and, did I mention, unreliable USB cables) but usually, the problem is somewhere else. The FPGA GPIO circuitry is very robust. Unless there is an external power source involved outside the bank voltage range, I doubt you'd manage to damage it even if you tried. I guess we all know those panic moments, like "oh no I've bricked / toasted the board" and then you have a coffee,
  8. Hi, for your toy example, you can safely enter set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_IBUF[1]] into the TCL command line and the warning should go away (this should cause no issues at low speed, say low MHz range) Without going into details, you may find that the most "simple" examples will become very complex (in a sense of getting down to the bottom what is actually happening on the FPGA) because you're deviating from standard design patterns (synchronous logic) that has information moving from register to register on a clock edge (and that clock needs to
  9. I think you'll save yourself much hassle if you don't share the same physical JTAG interface. Simply take a couple of GPIOs, connect them to an FT2232H minimodule or any other hardware interface, and run a fully independent physical interface. Otherwise, you're facing the problem that different software packages need access to the PC side of the JTAG box at the same time, and this usually does not work for the very simple reason that only one connection can be open at the same time on the PC side. I have successfully integrated my own logic to JTAG as it's ~5x faster than UART (see B
  10. Hi, please search the forum, it's fairly common and frequently resolved. Use a different cable, use a different computer (there is a high number of bad quality USB cables on the market; there are many unreliable PC ports e.g. because of bad polyfuses that have once tripped and never recover completely). You may have a bad module and there exists a newer hardware revision with improved decoupling caps but most likely the easiest way ahead for you is to get a quality cable and rule out issues with the USB port on the PC side.
  11. They probably put the option there for a reason, try to find one for yourself. It's easy to come up with relevant use cases, such as "drive a given voltage across some load". What will happen with a 50 ohms source?
  12. Hi, generally, the problem is that a 0 ohms output has theoretically an infinite power delivery capability, which is physically impossible. It may work correctly with some loads but not with others, and the transition area is ill-defined (e.g. peaks are clipped). A 50 ohms output has a controlled behavior for all (passive) loads. From a RF point-of-view, above some frequency the signal changes so rapidly that a reflection coming back from the other end of the (typically 50 ohms) cable is slightly delayed, compared to the generator output. Their interaction will cause unwanted RF
  13. one thought, you can configure 7 series 3.3 V inputs for 1.8 V input. There are hacks like using a series 10 kOhms resistor. It needs to drop 1.5 V so it'll sink 150 microamps into the ESD diode of the 1.8 V device at the other end. For proto-style development (and I guess that's what most of the one-size-fits-all-boards are all about) this is often acceptable.
  14. Check Trenz TE0725 family (remove one 0 ohms resistor for the bank voltage, solder a jumper wire to the large capacitor of the on-board regulator => VoilĂ , 1.8 V, even mixed with 3.3 V on the other bank if you want) The ICE 40 HX8K EVB (Lattice) is another board that can be rigged up for different VIO.
  15. Hi, maybe I'm missing something here but even a plain 640x480x60 VGA signal has a pixel clock of 25.175 MHz, against the XADC maximum sample rate (2 channels!) of 1 MHz?