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xc6lx45 last won the day on February 6

xc6lx45 had the most liked content!

About xc6lx45

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    RF / DSP / algorithms / systems design / implementation / characterization / final testing and creative abuse of Pedal Steel Guitars

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  1. high speed LVDS input on low-end boards Zybo/MicroZed/Z-turn

    Hi, I know nothing about your or your project, so don't get this wrong. But usually, FPGA projects based on board specs are "risky" (and maybe this is a euphemism). Making it work is one thing, but can you make sure there's a viable route from a "technology" concept demo to a marketable product? One problem with digital is, the fact that it works means very little. I can't distinguish between one fault in a billion years and one every 1000 hours. The former has sufficient margin. The latter fails miserably at the customer when some dust settles on the board. Spending a day reading 7-series select IO documentation might be a good plan. I'd do a quick reality check on the required timing accuracy between LVDS pairs. Sets off a red warning light for me. DRAM interfaces for that speed are routed quite carefully... If the interface is MIPI D-PHY based, search for that term and "CSI", there are a number of posts on the topic.
  2. Zybo Z7-20: FTDI DOA?

    Right... With the windows computer, you can open the device manager and check, whether the list of devices flickers (is rebuilt) when plugging in the unit. If so, there may be some old driver that is getting in the way. I haven't had issues with FTDI devices for years, but there may be still some of the old drivers lurking on peoples' computers... I don't know the SW ecosystem that comes with the board. Maybe you need to download the generic D2XX drivers (I'm just guessing but having those on a PC shouldn't cause any harm since they are so commonly found). If the device manager list does not flicker / show anything, it seems unlikely that a driver update would help.
  3. Zybo Z7-20: FTDI DOA?

    Check the cable, in case you haven't done so. It's a frequent cause of issues, even if the cable works with other components.
  4. Fir compiler core as a decimation

    I don't understand what you mean with "handle this filter delay in Xilinx". Causality requires the FIR filter to look 14 samples into the future before it delivers "the" output sample (formally: "group delay"). The implementation will need a little more, depending on what options you chose (e.g. "transposed" would be the fastest) Without coefficient-dependent optimization (odd-/even symmetry, halfband zeros), a FIR filter doesn't care about the "delay", it just spits out a weighted sum of input samples. But as said, I'm guessing at the question.
  5. Memory tutorial

    +1 for that. If possible, it'll save you a week, perform better and you maintain a board-independent design. I'm sure there are lots of FIFO examples out there... Attached one I use. Expect e.g. around 150 MHz on speed grade 1 Artix, possibly faster. Note, the memory is here ("inferred"): reg [DATABITS-1:0] mem[((1 << ADDRBITS)-1):0]; So there is no need to instantiate BRAM, it happens automatically. FIFO.v
  6. Writing to multiple parallel devices on one port should be easy by using multiple CS signals, but those three modules are all sensors. What would I do with the MISO pins?
  7. OK it's all sensors... I'd look at the thermocoupler data sheet and build a simple bitstream to read the temperature via GPIOs. In pseudocode this would be string clck= "010101010101010101..." string data= "001100000000110011... your SPI bitstream here" string read= "0000000x0x0x0x0x0x ..." the interesting bits long val = 0; CS_GPO = 0; (active) for (int ix = 0; ix < length(clck); ++ix){ CLK_GPO = clkk[ix]; MOSI_GPO = data[ix]; if (read[ix] == "x"){ val |= (MISO_GPI); val <<= 1; } } CS_GPO = 1; ... do something with val. The exact SPI timing (when to raise the clock and when to sample the output value) is usually described in the data sheet. Also the bit order for val needs to come from the data sheet. But, maybe someone more familiar with the ecosystem comes up with a nicer solution.
  8. BTW, this is probably borderline OT. But a USD 6 Dupont crimp tool from Ebay can be my best friend when I have to build a prototype "backplane" for 1/10 in modules:
  9. If "desperate", I guess you can do SPI by bit-banging GPIOs (haven't checked the schematic). Most likely there is a more elegant solution, though. If write-only, I think the Pi's SPI interface does not manage the CS pins, it's up to the user. So I could connect any number of write-only devices to one port. Cascading devices might be another option (device output A becomes device B input, it's just shift registers), but no idea how this would look in existing SW libraries. I've used it once on a "B" to talk to an FPGA - managed 60 MHz, by the way - but it's a while ago.
  10. Analog Discovery 2 with error "PLL not locked"

    Hi, just an observation: In the last screenshot, the message box reads "USB: 5.09 V 1058 mA". Isn't the USB 2.0 limit 500 mA? Seems a bit high...
  11. Basys2

    Most likely it's US export restrictions then. A topic where I'd tread really carefully. Or the next US trip gets an unplanned extension, food and shelter courtesy of the US government...
  12. Basys2

    Hi, Basys3 is Xilinx Artix-7 FPGA (XC7A35T-1CPG236C) . I believe it's the same as e.g. on the CMOD A7, which works with the free (webEditition) Xilinx license. The Basys2 page states The Basys 2 board works seamlessly with all versions of the Xilinx ISE® tools, including the free WebPACK™ In my understanding, you shouldn't need a paid license for either board. They may have shipped one for additional features (e.g. Microblaze and on-chip scope in ISE) but they aren't mandatory to work with the board. Try to generate a free ("WebEdition") license for Vivado (Basys3 board) and ISE (Basys2). Note, you may need to download an ISE version earlier than 14.7, according to the Xilinx download page. This is the link from Vivado license manager: And ISE. In the main window, they appear in the "Help" menu.
  13. How to move to older version of Vivaldo

    My understanding is that the license file is simply read by the software, and there is nothing else going on behind the scenes. If you'd uninstall and reinstall the same version, you'd be back where you started. This, however, is just an end user's view. If it means anything, my own .lic file is from 2014, and has served me through several Vivado (and most likely ISE) versions. Just a random thought: If you need to worry about 24 gigs of HD space, you may be facing an uphill battle in FPGA territory... People do custom builds with water cooling, overclocked quad-channel RAM, high-end SSD drives, and still it's too slow (and HD performance goes south unless there is plenty of empty space).
  14. How to move to older version of Vivaldo

    Hi, as far as I know you can install and keep multiple versions independently on the same PC, on the same license file. Xilinx groups them in the start menu by version number, that's no coincidence.
  15. disconnect_hw_server and connect_hw_server commands

    >> vivado15.1 Are you sure? This is my "Help/About Vivado" dialog of the latest free "webedition", which works for me without flaw for the CMOD A7: If really "15" it sounds like a fairly old version.