xc6lx45

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xc6lx45 last won the day on September 17

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About xc6lx45

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    RF / DSP / algorithms / systems design / implementation / characterization / final testing and creative abuse of Pedal Steel Guitars

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  1. xc6lx45

    What FPGA to buy..? What FPGA to buy..?

    Get a cheap Artix-7 board and spend a month full-time with it. You can see I'm not a sales guy but this >> and I'm a bit at a loss for what to get. is a dead giveaway. Assume it is MUCH harder than you think and the cheapest board allows you to run into most of the problems you'll encounter eventually. Consider it disposable so you don't lose time over worries that a single slip of a scope probe will blow your $3k board (I've seen that happen and I don't mean someone worrying about the possibility)
  2. xc6lx45

    reading XADC from user space

    Possibly this isn't helpful (I haven't used this combination myself) but can't you simply keep the file open, like /dev/snd for example on conventional Linux with legacy OSS sound?
  3. xc6lx45

    reading XADC from user space

    >> because opening/closing is taking in my case to much time. This just as an unspecific comment: A common solution for being able to start data acquisition "immediately" is to keep it running continuously, e.g. into a circular buffer. The start time then just becomes an index into the buffer. With typical industrial test equipment, it goes as follows: - I arm the instrument. It starts sampling into a buffer -Once sufficient pre-trigger samples are available, the instrument returns it's ready to accept a trigger -I trigger the measurement -internally, it looks back in time , according to its own processing delay etc and calculates the index into the buffer that corresponds to the trigger time We're not exactly beating causality but it's the next best thing... Also, I would think twice before using Linux for a problem that may turn out to be hard real-time. Those issues can become nasty when it looks like a sporadic glitch that I can solve later, and finally realize it's conceptual. At least study the capabilities of the IP / libraries you intend to use. The XADC itself is a fairly precise piece of hardware.
  4. xc6lx45

    fft spectrum analyzer on SOC

    and I was curious what brings you to that question. It's so difficult to come up with a meaningful homework problem (this one would be good), I don't want to carelessly ruin it 🙂
  5. xc6lx45

    fft spectrum analyzer on SOC

    homework problem?
  6. xc6lx45

    [NEED HELP] Fast Connection FPGA-PC

    You can probably make this work with UARTs if you use FTDI's own API (not Windows serial). If I remember correctly, they support officially 3 MBit/s and inofficially a lot more. You need 2.88 MBit/s plus protocol overhead. The same standard FTDI chip (e.g. .FT2232H) will give you up to 30 MBit/s through its MPSSE (high speed serial) mode. It's easier to connect one externally (e.g. "FTDI mini module" for $20) to the FPGA than to use the on-board FTDI chip of most boards. The latter is feasible (you have to go through the JTAG port) but the external-chip option is much easier to bring up. If you're after continuous (not burst) capture, setting up a PC for reliable real-time audio is a topic of its own...
  7. xc6lx45

    Best FPGA card to learn Network Message Processing

    Would a DP83848 as PHY give you the interface you need? If so, it's around USD 10 per port on a single breakout board (check ebay).
  8. Hi, 4 V does not seem right. I think you should supply the board externally (not through USB but use the external power input). Test with a different PC. Yes it's inconvenient but it may save you many hours. Or if not possible, put in at least a different USB card. USB is a mess, and creating a reliable high performance USB bus-powered design may be much harder than most people would expect ("high performance" because an FPGA is by far the most sophisticated electronics component ordinary mortals get to play with). For curiosity, read up on polyfuse memory, one root cause why those things can be near-impossible to debug. And the minimum number of cycles on USB connectors. And the recent crisis regarding low quality USB cables (and no one would have cared if they hadn't caused things to actually break).
  9. xc6lx45

    UART communication control with CMOD A7

    Hi, it is not as mysterious as it may look at first glance: OK there is one GPIO that needs to be set (only for custom JTAG!!) then it will work like any other Xilinx/FTDI combo. From a functional point-of-view, look at Papilio Pro schematics on Gadget Factory, it should be identical (there are some buffers, just pretend they don't exist). The UART is one electrical wire FTDI-to-FPGA and one other wire vice-versa. What you're asking for is a protocol feature. This doesn't exist in hardware (at least not with the "conventional" two-wire UART interface. The FTDI chip might have additional signals e.g. CTS and RTS that are rarely connected on "conventional" Xilinx FPGA boards). I suspect you have a driver issue. Teraterm should never crash, it just gives you a black screen and no echo. If you do a trivial FPGA design and route Rx to Tx on the FPGA, Teraterm will echo back any characters you type. This is usually my first step to make UART work (if you happen to have another standalone FTDI board around, you can use a jumper wire as an experiment. Echo works with the wire connected and stops when disconnected)
  10. try project manager: "IP catalog". Search for "XADC", the "XADC wizard" pops up. Double-click to start. On the "Basic" tab, use the "DRP timing options".
  11. xc6lx45

    XADC and the FFT

    The format isn't understood by Matlab's "load" function. Use a text editor, delete the first two lines and replace "," with space or tab, then it should load the file.
  12. xc6lx45

    XADC and the FFT

    BTW it should be "20*log10(fftshift(abs(fft(...)))) not 10. If you're dealing with voltage, current, wave quantities, anything that gets converted to physical power by squaring, use 20 log10 =2*10*log10(x) = 10*log10(|x|.^2)
  13. xc6lx45

    Lock-in amp + AD2 = Signal improvements?

    Hi, maybe you should explain a little more what you're trying to achieve. One general option is to record the signal and then do Fourier transform in Matlab or the like. Possibly you need to identify what is the bottleneck (is your detector too noisy, or is its bandwidth simply too wide? The latter can be easily fixed, see above...)
  14. xc6lx45

    heatsink for Arty Z7-20

    Hi, maybe of interest, here is a similar question: https://forum.digilentinc.com/topic/15809-using-a-heatsink-on-my-zynq-7000-not-sure-what-kind-of-thermal-thing-to-use/#comment-38696
  15. xc6lx45

    Arty A7-35T IPs for communication with a Linux PC

    Hi, using AXI without a processor is unnecessarily complex. In comparison, the UART functionality is almost trivial. You should be able to reach maybe 2 MBits / second. For comparison, JTAG goes up to 30 MBits / second but it's not as easy. Below some very old code from a very dusty corner of my hard drive. You have to set "nBitCycles" to the length of one bit in clock cycles, e.g. for 9600 baud and 100 MHz clock it's 100e6 / 9600. The easiest way to test is to link serialRx/out_byte to serialTx/inByte, serialRx/in_strobe to serialTx/inStrobe. Then it'll echo back all data. // note: if rx is an external (asynchronous) input, it must be registered first module sk61_serialRx(clk, in_rx, out_byte, out_strobe); input clk; input in_rx; parameter nBitCycles = 0; reg [31:0] count; reg [3:0] state = 0; reg [7:0] data; output reg out_strobe; output [7:0] out_byte; assign out_byte = out_strobe ? data : 'bx; always @(posedge clk) begin out_strobe <= 1'b0; // non-final if (state == 0) begin if (!in_rx) begin state <= 1; count <= $floor(nBitCycles/2+0.5); end end else if (state == 10) begin // stop bit // wait for nominal sampling instant if (count != 0) count <= count - 1; else if (in_rx) begin // after nominal sampling instant, wait for line to go high // => ready to signal next byte with falling edge // => restart state <= 0; count <= 'bx; data <= 'bx; end end else begin if (count != 0) begin // start bit count <= count - 1; end else begin // data bits data <= {in_rx, data[7:1]}; state <= state + 1; count <= nBitCycles; if (state == 9) begin // final data bit out_strobe <= 1'b1; end end end end endmodule module sk61_serialTx(clk, out_tx, in_byte, in_strobe, out_busy); parameter nBitCycles = 0; input clk; output out_tx; input [7:0] in_byte; input in_strobe; output out_busy; reg [31:0] count; reg [3:0] state = 0; reg [7:0] data; assign out_tx = (state == 0) ? 1'b1: // ready (state == 1) ? 1'b0: // start bit (state == 10) ? 1'b1: // stop bit data[0]; // data bits assign out_busy = (state != 0); always @(posedge clk) begin // correctly timed, in_strobe appears only during idle state (0) // however, if echoing data from a UART, small timing error may cause // a new byte to start already during the stop bit // This implementation does not prevent retriggering at any time, // but this will cause garbled data. if (in_strobe) begin count <= nBitCycles; state <= 1; data <= in_byte; end else if (state != 0) begin if (count == 0) begin count <= nBitCycles; // (non-final) state <= state + 1; // (non-final) case (state) 1: begin // startbit end default: begin // data bits data <= {1'bx, data[7:1]}; end 10: begin // stop bit state <= 0; count <= 'bx; data <= 'bx; end endcase end else begin count <= count - 1; end end end endmodule