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xc6lx45 last won the day on January 1

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About xc6lx45

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    RF / DSP / algorithms / systems / implementation / characterization / high-speed PA test and creative abuse of Pedal Steel Guitars

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  1. Hi, usually I'm with you on avoiding "wizardry" but there is a risk that you're venturing out into uncharted waters. It's not a trivial subsystem, at least read the manual for the block - just kiddin' it's 114 pages Or not. Maybe check page 77, the paragraph at the bottom. Myself, I would still use the wizard, if only for the jitter estimate (it can vary greatly, depending on settings). Also consider LOW instead of OPTIMiZED for improved input jitter rejection, as long as the generated clock phase relative to the input clock does not matter. And it may help a little to cascade two stages, especially if the clock is meant for something else than driving digital logic.
  2. Hi, it's not handled through the constraints file. This would tell Vivado that you already have a faster clock and feed it into the chip. What you should look at is the "clocking wizard". On Vivado main screen, locate "Flow manager" / "PROJECT MANAGER" (left side of screen) There is an entry "IP catalog". Click it. Look under "FPGA features and design" for "clocking wizard". Double-click it and a GUI opens. In "clocking options", set "MMCM" (PLL won't work from 12 MHz input clock). Change "input frequency" from 100 to 12 (MHz). Under "output clock", enter your desired clock frequency. For a start, you don't need any other ports than "input" and "output" (disable "reset" and "locked"). In your RTL code, feed this block the 12 MHz crystal clock.
  3. Just a thought: If you use a plain FT2232H (e.g. via this module) you can bit-bang one bank of 8 bits at 1 MHz (max. clock rate 500 kHz). It's relatively straightforward to program. The achievable roundtrip latency "in production" is 125 microseconds or even one third less under lab conditions (because "ping-pong-ping" can be made to fit in one USB 2.0 8 kHz microframe if the PC adds no delay).
  4. xc6lx45

    State machine vs Microblaze MCU

    Hi, I suspect the complexity is far below the break-even point where the more complex architecture pays off. Making it work may even take a comparable amount of time, but you'll have to manage a design in more dimensions (user RTL, MCU, embedded code) compared to a simple "flat" RTL design. The MCU may create several problems (e.g. need for FIFOs, clock domain crossings) that can be avoided completely with a FSM. If you haven't done this repeatedly, it may take a little time to get fluent with coding FSMs in RTL. Until then, you may find you're biased towards "traditional" procedural programming, even though a plain Verilog FSM is often more concise and intuitive (opinion). For learning, why not try both. Bringing up a quick-and-dirty functional prototype shouldn't be that much work. And check what happens to the project build time when adding the MCU. Software changes are quick, though.
  5. >> having about 60uF of ceramic decoupling goodness Maybe it's even more a question of ESR than capacitance. Ceramic if money doesn't matter (e.g. Mouser: 22 µF: €4..6). The typical solution are staggered capacitors, with a quick look at the datasheet for the self resonance frequency in the impedance curve. I do this for RF (try to get a quality short at n GHz...) but if I had to make a blind guess, I'd use two orders of magnitude, e.g. 10 µ, 100n, 1n and with a nervous glance at my Voodoo doll, 10p. The CMOD A7 is reported quite frequently (possibly because it's one of the most attractive boards) but I can tell that I've run into the same issues with FTDI's reference module for the 2232H. The chip just shuts down if it doesn't like what it sees on VCC. It took a long Friday night in the lab to prove without doubt that our system is sensitive to USB cables. We changed the design and shipped with non-detachable cable. Zero issues so far.
  6. xc6lx45


    I'm wary of Matlab magic converters. Maybe they actually work and generate results that fit into an entry-level FPGA(!). If so, I'm the wrong guy to comment. That said: If FPGA is a must, I would try to renegotiate the project scope to use a MCU (softcore or better the ARM on a Zynq board) with FPGA accelerators. Then implement the prototype in plain C. Which you can test on a standard PC. Then strip it down so it runs (very slowly) on the target platform's processor. Then create FPGA accelerators for select functions and test them independent of the algorithm. Maybe FFT is already enough (the MCU should be handle the log() with a fast approximation function). Now if I had to make a project plan for a newcomer working independently, I'd say a month, or two to be on the safe side...in reality probably three.
  7. xc6lx45

    related to ' c ' language

    Hi, I think you'll need to add a terminating zero to the string (C string convention), otherwise junk may appear directly afterwards.
  8. And they call it progress... As a tiny bit of good news, inference allows some vendor-independent coding e.g. mapping of multipliers and block ram with the necessary pipeline registers. Well, to be honest, I haven't put it to the test going from X to A or vice versa. But to be honest, I think the hard-macro approach is the only way to go if performance matters. An FPGA is not a "standard cell" ASIC and those two worlds are drifting further apart.
  9. xc6lx45

    GPS Pmod

    I must say I share D@n's opinion here. What I would do is start with a plain serial port. Create a dumb (non-clocked) FPGA design that routes the FTDI chip's UART pins to some GPIOs, and hook up the GPS module. Alternatively, use a standalone FTDI-to-UART module or equivalent. Fire up teraterm (e.g.) on the PC, open the COM port, set the correct baud rate. Check that the GPS module responds as expected. Check that the message format is exactly as you expect it. I suspect this assumption >> it seems, that the given functions from digilents pmodgps.h heather are doing already the right stuff won't hold. What you're trying reminds me of the old joke about a gynecologist retraining as a car mechanic🙂
  10. xc6lx45


    Hi, >> "formal port ja_pin3_io of mode inout cannot be associated with actual port ja_pin3_io of mode out " is this maybe just a typo?
  11. xc6lx45

    Configuring dvi2rgb and rgb2dvi IP blocks on PYNQ board

    OK those critical warnings are related to the VCO, not timing itself. So what I wrote above regarding P&R doesn't apply here.
  12. xc6lx45

    Configuring dvi2rgb and rgb2dvi IP blocks on PYNQ board

    >> that timing requirements may throw a critical warning but the design will work anyway This sets off red flags for me. Just speaking for myself, I wouldn't ever assume this. The problem is that the attempt by P&R to do the impossible may wreak havoc on the rest of the design so it doesn't necessarily "fail soft"
  13. xc6lx45

    Time interval measurement between two pulses

    Hi, generating the frequency is not the problem: The FPGA has PLLs of its own, the board clock frequency does not directly matter for this question. However, designing at 450 MHz will be a specialist job, most likely using a "SERDES" IO block at the input (there is dedicated hardware that eats up e.g. 8 bits at high frequency, and the downstream logic can run at 1/8 the fast rate). I don't think a straightforward counter would work (speed of carry chain). Alternatives might be shift-register based or one-hot FSM (this just from the top of my head). You'll find that FPGA tools require patience under the best of circumstances. Pushing performance to the limit can make design iterations very slow. And, you may have better luck with a Spartan 7 (e.g. CMOD S7 board) than an Artix (e.g. CMOD A7 board). Kintex and Virtex should make this job easier but double-check the required tool licenses. You don't need to own the board to synthesize a test design and get the timing report (e.g. with a 30-day eval version).
  14. xc6lx45

    Nexys2 suddenly stopped working with custom bit files

    Hi, those are just generic things to try. I hope you'll get more specific advice from the official support. is it possible that some obscure options in your ISE project or the constraints file have been changed? I'd try a new copy of the constraints file and download or create a project from scratch. Reinstalling ISE might be another thing to try, just to rule out the possibility that it got damaged. I would get a different USB cable and port, even if the original bitfiles work with the one you've got.
  15. xc6lx45

    FFT / iFFT / RS - Basys3

    I suspect your "ifft" is in reality a conjugated fft Mathematical background (behind this theory and conventional fft-based crosscorrelation): In an FFT-less world, you'd use a so-called "matched filter" as optimal detector that convolves with a time-reversed replica of the known signal (see first line here. Never mind "conjugated" since you have real-valued data). FFT does the convolution. Conjugation in the frequency domain is equivalent to time reversal in the time domain.