aksaltaaf

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  1. aksaltaaf

    Rule violation

    ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 20 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: vgared[3:0], vgagreen[3:0], vgablue[3:0], ja[7], ja[6], ja[5], ja[4], ja[0], clk100mhz, hsync, vsync. ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 20 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: vgared[3:0], vgagreen[3:0], vgablue[3:0], ja[7], ja[6], ja[5], ja[4], ja[0], clk100mhz, hsync, vsync. INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings
  2. I tried to connect nexys4 ddr board and basys3 board using pmod directly. Data is going out of nexys4 board but basys3 is not taking that data.
  3. I would like to transfer data from nexus 4 DDR board to basys 3 board using pmod. What connection I have to do?