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Everything posted by sLowe

  1. Hey Shruthi, I'm linking your other post where I gave some starting points for people looking. Lets us know if you need more help. -Sam
  2. Hey Shruthi, I believe the correct way to do this is by making a .txt or .csv file and then loading that into the XADC IP block under ANALOG Sim File Options on the basic tab. The formatting of these files is discussed on page 41-43 of the product guide linked below. I've never done this before but if you run into any walls post here again and we can help you figure this out! -Sam
  3. sLowe

    Map problem on Nexys4DDR

    Hey Anding, I think this is the correct approach. Off of a couple xilinx support threads a flow similar to this is suggested to get the tools to see that .ucf file. Seems like this stems from creating the ip from the project manager instead of a standalone core generator. The link you found is much easier to follow and should be used. For future readers that link is copied from an earlier post below. I will also put in a note on the ram2ddr component wiki page. Thanks for the info!
  4. Hey Moez, All of our Artix-7 and Zynq boards have this capability through the xadc embedded on the FPGA. Here is a link to the XADC datasheet. If this satisfies your requirements, one of the xadc reference projects located on our wiki would be a good place to start. This is for the basys 3 -Sam
  5. Hey Antek, A quick solution that comes to mind would be to make your own bus truncate with HDL and then generate the schematic symbol for it. You would then place your block in between your multiplier and your adder in is 35 bit logic vector and out is 16 bit logic vector out(15 downto 0) <= in(15 downto 0); You could also put in an overflow indicator in case your multiply goes above 65k. - Sam
  6. The way we tackled that was setting a 1V sin wave to be offset .5 V which gave us the ability to just use unipolar mode. However, it should be as easy as opening the xadc wizard and change the modes on the channel sequencer page by checking Bipolar but I have never tried it before. I was looking at the following Xilinx documents -Sam
  7. Hey you, Tommy is right, the XADC will measure 0 to 1 V (single-ended) or -.5 to .5 V deferentially. The pins themselves can tolerate up to 2V but will saturate the ADC at 1V. It would be interesting to see if they could measure 1-2V by setting the N pin to 1 V and the P pin to 1-2V. Pin max ratings XADC guide -Sam
  8. The wiki should now be up to date. The BSD can be found here -Sam
  9. Its very weird that your board reads in as a xc3s500t device. Rev. D boards are 250t. When I attach my basys2 through impact's boundary scan wizard, I get the following console output. So we can see that it reads in as a 250 device and not a 500. I would recommend that you reinstall the cable drivers and try again. If that does not work and you are still seeing the wrong device, maybe get in touch with Digilent costumer support. -Sam INFO:iMPACT - Digilent Plugin: JTAG Port Number: 0 INFO:iMPACT - Digilent Plugin: JTAG Clock Frequency: 4000000 Hz Attempting to identify devices in the boundary-scan chain configuration... INFO:iMPACT - Current time: 11/12/2015 12:08:33 PM PROGRESS_START - Starting Operation. Identifying chain contents...'0': : Manufacturer's ID = Xilinx xcf02s, Version : 13 INFO:iMPACT:1777 - Reading C:/Xilinx/14.7/ISE_DS/ISE/xcf/data/xcf02s.bsd... INFO:iMPACT:501 - '1': Added Device xcf02s successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- '1': : Manufacturer's ID = Xilinx xc3s250e, Version : 1 INFO:iMPACT:1777 - Reading C:/Xilinx/14.7/ISE_DS/ISE/spartan3e/data/xc3s250e.bsd... INFO:iMPACT:501 - '1': Added Device xc3s250e successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- done. PROGRESS_END - End Operation. Elapsed time = 1 sec.
  10. Oh in that case, try deleting your MIG.ucf file since the .ngc should constrain the ddr pinouts. The .UCF is useful when you go through the MIG yourself and have to specify the ports used. I personally have never used the .ngc file so I dont know this for sure. I in the past have just gone through the wizard.
  11. Hey BlazeMicro, You should not have to put the ddr pinouts in your master UCF if you are using the MIG. You should use the MIG project files to configure the mig and the ram2ddr component will instantiate it within itself, -Sam
  12. sLowe

    Nexys video looper demo

    Hey, What are you plugging into the line in to record from? I have successfully gotten this demo running before. Also if you press record do you get the progress bar? -Sam
  13. Hey Michael, I don't know why Vivado is doing this. In the meantime you can open up the clocking wizard, click on the output clock tab, and set reset polarity to be active low. The board file seems to define the reset pin as active low but I will keep investigating. Hope this helps, - Sam
  14. Hey Serge, Look like your device thinks it is a 500 device instead of 250 or 100. What is the rev on your basys 2? It can be found below the white rectangle on your board. It would be interesting to try to set your part in the project settings to xc3s500e. Thanks, Sam
  15. Hey Benjamin, I ported the Nexys4-DDR XADC reference project to ISE 14.7 and posted it to the XADC reference project wiki. The page can be found here The direct link to the ISE project is (found at the bottom of the wiki page) Hope this helps! I will keep an eye on this stream if you have any issues with the ISE project. -Sam
  16. Hey Bob, That's ok that you didn't have an ARTY folder. Vivado only comes with a couple of their dev. boards by default. It probably solved your connection issues because Vivado uses the board part in the board file to figure out who to talk to in the hardware manager. Good luck on the demo! -Sam
  17. Also fixed the XADC demo to have the correct device. -Sam
  18. Hey Leon, I fixed the project. Thanks for catching this! The project should be fixed on the wiki, I'm going to check all the other reference projects now. Thanks, Sam
  19. Hey Michael, The new board files can be found here You are looking for the arty/C.0 to replace your B.0 folder in your Vivado installation folder. You may need to delete the B.0 folder and restart Vivado Hope this helps! -Sam Lowe KG7VYM
  20. The problem is that you are sampling the spi signal at clk and not sclk. You probably got an output that looked like all the leds were doing the same thing. If so, you were most likely picking up a single data bit. The fix is to change all the clk to sclk in you state machine. The code I ended up is below. Other things I did included flipping the polarity of the clr signal since I just used a button. Also I removed the pullup identifiers for the Pmod pins in my UCF since SPI doesnt require them. Ill keep an eye on the page in case you need any more help! -Sam LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY SPI3 IS PORT( clk : IN std_logic; clr : IN std_logic; dout : IN std_logic; led : OUT std_logic_vector( 7 DOWNTO 0 ); sclk : INOUT std_logic; cs : OUT std_logic ); END SPI3; ARCHITECTURE SPI3_be OF SPI3 IS TYPE state_type IS( idle, adc_r, adc_w ); SIGNAL state : state_type := idle; SIGNAL cnt_sclk : INTEGER RANGE 0 TO 49; SIGNAL newsclk : std_logic := '0'; SIGNAL cnt_cs : INTEGER RANGE 0 TO 1000; SIGNAL newcs : std_logic := '1'; SIGNAL data : std_logic_vector( 7 DOWNTO 0 ); SIGNAL cnt_data : INTEGER RANGE 1 TO 16; BEGIN sclk <= newsclk; cs <= newcs; clkdiv : PROCESS( clr, clk ) BEGIN IF clr = '1' THEN cnt_sclk <= 0; cnt_cs <= 0; newsclk <= '0'; newcs <= '1'; ELSIF clk'EVENT AND clk = '1' THEN IF cnt_sclk = 49 THEN newsclk <= NOT newsclk; cnt_sclk <= 0; ELSE cnt_sclk <= cnt_sclk + 1; END IF; IF cnt_cs = 1000 THEN newcs <= NOT newcs; cnt_cs <= 0; ELSE cnt_cs <= cnt_cs + 1; END IF; END IF; END PROCESS clkdiv; FSM : PROCESS( sclk, clr, state ) BEGIN IF clr ='1' THEN cnt_data <= 1; data <= "11111111"; ELSIF sclk'EVENT AND sclk = '1' THEN CASE state IS WHEN idle => IF newcs = '1' THEN state <= idle; ELSIF newcs ='0' THEN state <= adc_r; END IF; WHEN adc_r => IF cnt_data >0 AND cnt_data <4 THEN cnt_data <= cnt_data + 1; state <= adc_r; ELSIF cnt_data > 3 AND cnt_data <12 THEN cnt_data <= cnt_data + 1; data( 11 - cnt_data ) <= dout; state <= adc_r; ELSIF cnt_data > 11 AND cnt_data <16 THEN cnt_data <= cnt_data + 1; state <= adc_r; ELSIF cnt_data = 16 THEN state <= adc_w; END IF; WHEN adc_w => led <= data; cnt_data <= 1; state <= idle; END CASE; END IF; END PROCESS FSM; END SPI3_BE;
  21. sLowe

    Genesys DDR2 + ISE

    Hey Kimxin, I don't know if any simple example exists for using the MIG. I think the Nexys4-DDR ram2ddr component should expose you to using the DDR2 MIG interface. You may even be able to use that component if your design doesn't need to operate very quickly. I haven't worked directly with the MIG to read and write but I think a good place to start looking would be the ram2ddr component and the MIG user guide. (Found by opening the IP and clicking User Guide). If these resources don't help too much, I can spend some time to try and get a simple working demo. Although now that school has started back up it may take a little bit of time. Good luck!
  22. sLowe

    Jtag HS3

    Hey Jonathan, Luckily the zc702 schematic shows the connections and it looks pretty close to what you have. Some things did catch my eye though. I looks like you pull up your signals to 3.3 V instead of VADJ like they do and they actually have a Bidirectional Voltage-Level Translator to change the 3.3 V signals to Vadj as all the signals terminate on Bank 13 (which is a Vadj bank) This would probably cause some problems. Here is the schematic The programming circuit is located on page 35 and Bank 13 is on page 4. I will keep looking around but hopefully this helps in the meantime!
  23. sLowe

    JTAG SMT2 chain limit

    Hey Dan, It seems like the only real limiting factor is clocking signal integrity. Here is an answer from Xilinx to a similar question not using the JTAG-SMT2 module but has some good tips. They were having trouble getting consistent results with more than ten devices. The Xilinx answer goes into how they use a buffer to drive the clock nets to run 100 devices. So with some extra electronics, the JTAG chain can get pretty large! Would be interesting to try to empirically see how many devices the SMT2 could reliably drive alone. Hope this helps! Sam
  24. Hey Chris, I haven't played with this stuff too much but while reading up on the subject I came across this page It seems to go pretty in depth and may help you out. This guy is running Xillinux on a Zedboard but it should be pretty similar for Ubuntu. Using this method, you could try to compile it on your board. -Sam
  25. Hey! As far as ARM Cortex M0 goes, Digilent only provides the hardware. We haven't worked a lot with it in house. But we would still love to help! Do you know what the debugging interface is on the cortex M0 is? There may be a way to port out the correct pins to a Pmod header to debug it with a third party tool. I've started poking around on the ARM site and will let you know if I find anything. -Sam