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Everything posted by sLowe

  1. sLowe

    Nexys4 DDR ethernet

    Hello, The ethernet lite IP uses the lwip stack. Its wiki can be found here. You should be able to use the same hardware setup as the servers demo plus your Pmod connection. The hard part will be determining how to get data straight to your computer. The way I can immediately think of (I'm by no means an expert) is to set up a "server" on your computer that waits for data coming in to its socket then prints it out on arrival. You would then need to figure out how to act as a client from your program to send the server data. If you just want to be able to query your board for data at a constant rate, you may want to just use the server demo you built and instead of sending back an echo, grab data from your Pmod and send that. Long story short there isn't a simple demo that basically replaces a UART connection with ethernet but with some digging it shouldn't be too hard. The tutorial mostly focuses on the hardware setup which is mostly dealing with building the base design for a microblaze project. Maybe more explanation of why things are set up the way they are could be something to add to the tutorial going forward! Id be happy to explain any parts you don't understand. -Sam
  2. Hey Andrew, Looks like that is the part from ON Semiconductor listed below NSQA6V8 SOT-323-5 Here is a link to digikey For packaging, I'm pretty sure SOT-323-5 is the same as SOT-353. Hope this helps! -Sam
  3. I'm pretty sure the basys3 comes packed with the GPIO demo which can be found here. You can obtain the bit file by generating and building the project. -Sam
  4. sLowe

    XADC demo

    Hey I think you are really close. Try using this .xdc in your project. My project is working now with this xdc. If you are getting .12 that seems to be the floating value. The project uses switches to select the channel. ad11 is connected to the display when sw0 and sw1 are both up. I will also reupload the project to the wiki. Thanks for the catch! -Sam # Clock signal #Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ set_property PACKAGE_PIN E3 [get_ports CLK100MHZ] set_property IOSTANDARD LVCMOS33 [get_ports CLK100MHZ] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK100MHZ] # Switches #Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 set_property PACKAGE_PIN U9 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] #Bank = 34, Pin name = IO_25_34, Sch name = SW1 set_property PACKAGE_PIN U8 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] # LEDs #Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 set_property PACKAGE_PIN T8 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] #Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 set_property PACKAGE_PIN V9 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] #Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 set_property PACKAGE_PIN R8 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] #Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 set_property PACKAGE_PIN T6 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] #Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 set_property PACKAGE_PIN T5 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] #Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 set_property PACKAGE_PIN T4 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] #Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 set_property PACKAGE_PIN U7 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 set_property PACKAGE_PIN U6 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] #Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 set_property PACKAGE_PIN V4 [get_ports {led[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] #Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 set_property PACKAGE_PIN U3 [get_ports {led[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] #Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 set_property PACKAGE_PIN V1 [get_ports {led[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] #Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 set_property PACKAGE_PIN R1 [get_ports {led[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] #Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 set_property PACKAGE_PIN P5 [get_ports {led[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] #Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 set_property PACKAGE_PIN U1 [get_ports {led[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] #Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 set_property PACKAGE_PIN R2 [get_ports {led[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] #Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 set_property PACKAGE_PIN P2 [get_ports {led[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] #7 segment display #Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA set_property PACKAGE_PIN L3 [get_ports {seg[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] #Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB set_property PACKAGE_PIN N1 [get_ports {seg[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] #Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC set_property PACKAGE_PIN L5 [get_ports {seg[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] #Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD set_property PACKAGE_PIN L4 [get_ports {seg[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] #Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE set_property PACKAGE_PIN K3 [get_ports {seg[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] #Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF set_property PACKAGE_PIN M2 [get_ports {seg[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] #Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG set_property PACKAGE_PIN L6 [get_ports {seg[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] #Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP set_property PACKAGE_PIN M4 [get_ports dp] set_property IOSTANDARD LVCMOS33 [get_ports dp] #Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 set_property PACKAGE_PIN N6 [get_ports {an[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] #Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 set_property PACKAGE_PIN M6 [get_ports {an[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] #Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 set_property PACKAGE_PIN M3 [get_ports {an[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] #Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 set_property PACKAGE_PIN N5 [get_ports {an[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] #Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 set_property PACKAGE_PIN N2 [get_ports {an[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] #Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 set_property PACKAGE_PIN N4 [get_ports {an[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] #Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 set_property PACKAGE_PIN L1 [get_ports {an[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] #Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 set_property PACKAGE_PIN M1 [get_ports {an[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] #Pmod Header JXADC #Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P set_property PACKAGE_PIN A13 [get_ports {vauxp3}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxp3}] #Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P set_property PACKAGE_PIN A15 [get_ports {vauxp10}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxp10}] #Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P set_property PACKAGE_PIN B16 [get_ports {vauxp2}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxp2}] #Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P set_property PACKAGE_PIN B18 [get_ports {vauxp11}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxp11}] #Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N set_property PACKAGE_PIN A14 [get_ports {vauxn3}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxn3}] #Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N set_property PACKAGE_PIN A16 [get_ports {vauxn10}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxn10}] #Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N set_property PACKAGE_PIN B17 [get_ports {vauxn2}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxn2}] #Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N set_property PACKAGE_PIN A18 [get_ports {vauxn11}] set_property IOSTANDARD LVCMOS33 [get_ports {vauxn11}]
  5. sLowe

    XADC demo

    Its ok to use them as single ended pins but AD11N needs to be wired to ground. But it seems like your not getting your signal tied to the xadc core. In your xdc make sure your uncommented xadc lines match the ones below. set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { vauxn11 }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { vauxp11 }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] A quick check to see if the rest of the project is working is to make the "data" wire a reg and set it to a value not zero. This should cause the seven segment and leds to display something else upon startup. Ill try to build the project here shortly -Sam
  6. The Atlys can definitely be a board to use for audio processing. I personally haven't used it but once you can figure out how the LM4550 AC ‘97 audio codec works, it should be simple to put some effects into the stream. I tried to download that project but it seems to have been removed. A good project to look at may be the looper demo for the nexys video here The only things you would need to change would be the audio codec interface and possibly the DDR interface. It is a pretty large project but I assume a reverb affect requires some memory applications. Hopefully you have already got this issue resolved since I am realizing this post is from july. -Sam
  7. sLowe

    XADC demo

    Hey Manas, I think you don't have the correct analog channel. The demo is set up to run on the channel AD11 which would be pin column 4 on the XADC header, No lights or display is also weird since a floating value should not pass a straight zero. Does your seven segment display light up at all? (showing all zeros) -Sam
  8. Try making your dma burst size smaller in the hardware design. That mostly got rid of that nasty static in fnAudioPlay for me. I think this is caused by the Zynq axi bus not being at the same version as the PL AXI bus.
  9. Hey David, So just successfully did this implementing a clock divider driving an LED. I didn't realize the Zybo's SDK programming guide is not correct. Ill be updating it soon to match the Zedboards guide here. Ill quickly explain my steps below though since I don't know how fast Ill be able to fix it. 1. create a base zynq design and verify. (create block diagram, add zynq core, run block automation, connect FCLK_CLK0 to M_AXI_GP0_ACLK) 2. generate the top wrapper from the block design and don't let vivado auto update the wrapper. 4. edit the top file to include your HDL module 5. generate bitstream 6. file -> export -> hardware (include bitstream) 7. open sdk 8. file-> new -> application project 9. select FSBL and create project 10. Xilinx tools-> create boot image 11. choose file output location 12. add file -> <FSBL>.debug/<FSBL>.elf' 13. add file -> hardware platform/.bit 14. click ok 15. xilinx tools -> program flash and choose your exported .bin file 16. switch jumper to qspi and reset board I'm pretty sure that is the rough procedure I used to get this working if it still doesn't work stay tuned for the new guide. Ill also include my small proof project. -Sam
  10. That is very interesting that the DDR settings are different. Do you know which settings have changed? Some of them make larger differences than others. I also don't know why this would make one board work and another not work. A DDR problem would explain why your program isn't running correctly and I would definitely focus my attention there. Maybe flip through and find the differences in the DDR and maybe we can figure out what is going on.
  11. Hey Lyao, Yup your math checks out! I was looking at the xdc to make sure there were 49 ck pins and with the spi header it adds up. -Sam
  12. Unfortunately for pure PL designs on the zybo, you are still required to run an SDK project to program it. The QSPI is hardlined to the arm core so you will have to create a boot.image like the process shown here but you just wont have an SDK project to include. You will only need the fsbl and the bin file. -Sam
  13. Hey, A quick test to see if your UART is connected properly or if there is a fault is to send a signal from your computer and see if the Tx led is lighting up at all. I don't think that is the main problem though as it looks like your program isn't even executing. A couple thoughts.... - Can you press the stop button? I have a feeling you will get a telling error message. - Can you debug the program? If so try to find where it is stuck at Ill check back here to see if we cant figure this out before declaring the board's JTAG dead. -Sam
  14. Hey digizybo, You can go back into vivado and select help->add design tools or devices and select SDK to easily install SDK 16.2 -Sam
  15. Hey Axe, The "quick fix" for your led problem is that you aren't specifying that they are outputs before you write to them. Place this line after your XGpio_initialize call. XGpio_SetDataDirection(&led, 1, 0x00); I don't know why your UART isn't working. Are you sure you are successfully programming the FPGA before you program yourself? When I just built this project it worked. Another check would be to see if the RX light flicks on at the start of your program when you expect UART transmissions. Your UART terminal should be set to a 115200 baud rate. Hope this helps, Sam
  16. This looks like a serious limitation of the BRAM controller IP in Vivado. The best answer I could find to this problem was found on this thread. Basically they generate a wrapper for the block design after making the axi bus external. Then manually attach a generic BRAM IP to the bus in a top file above the block design. I haven't tried it but it may be worth a try if you are still struggling. Good luck!
  17. Hey dCas, You should be able to closely follow that pdf with the Nexys 4. The main differences will be the part in the project settings and the UCF file used with the Nexys 4. Other than those two things, you should be able to recreate all of those projects. On top of that there is some more room for expansion since the Nexys 4 has 2 7 seg displays and more switches and leds. Using the Nexys 4 also opens you up to using Vivado however that wouldn't follow very closely with the PDF's when it comes to simulation and programming. I've personally found Vivado to be a little easier to pick up than ISE. (simulator and hardware programmer are integrated) Ill keep an eye out to see if you have any more concerns. -Sam
  18. You should be able to instantiate additional BRAM by placing a BRAM controller IP in your block design. When you run block and connection automation, you should be able to use this block memory for your program. Just make sure it gets connected through a memory interconnect.
  19. Id love to see your project! Also @Axe may want to take a peek at your non microblaze project too!
  20. Can you try to find some audio that you can tell left from right? I fear that you are just contacting both channels of your headphones to only one channel of the headphone jack. I'm betting the problem is something in the codec writes or the I2S stream. Do you go through the same writes that I did above? I also wrote the 8th bit of regs 2 and 3 to 0 when I tested it.
  21. Weird my project seems to be playing in both earphones when I record music from my computer into the line in port and play it out. A couple things to check though. Is your input audio stereo? If you are using the mic input that is only mono
  22. Hey Axe, I think the following flow will get your program running using the bitstream you just created 1. export your hardware by selecting File->export->export hardware make sure include bitstream is checked and press ok 2. launch SDK by selecting file launch SDK and press ok 3. Select file->new->application project name the project then click next 4. select hello world from the list and let sdk generate a hello world project 5. delete your helloworld.c file 6. copy in the .c and .h files from the guthub sdk folder (you can drag and drop) 7. program the FPGA and run your project .elf file on system debugger However if you are fine using the hardware platform shipped with the project (it should be the same) you can just import the sdk folder from the github as a workspace into SDK and follow the steps on this guide. -Sam
  23. That is a good catch! Thinking about it, this just sets both of the volume registers to the same value twice. Since I want them at the same value, the write to reg3 is not needed. This shouldn't cause any problems with the function of the design though. Ill probably go back and change it to assign them separately in case someone in the future wants different channel volumes. Thanks! -Sam
  24. sLowe

    I2S IP core and AXI DMA

    Nice that's awesome and I'd love to see your project! One thing I found out that may be helpful is that I found if the DMA max burst size is over 16 bytes, on playback there was a noticeable pop. I think this comes from the Zynq high performance port not being up to the current AXI standard and doesn't support large burst sizes. -Sam
  25. The PmodI2S was built to sample at 48 or 96 kHz so if you don't mind oversampling a bit, there should be no problems. 24 and 16 bit audio should work fine. Also you can drive the serial clock at 4/8/16 kHz and virtually sample at those rates. -Sam