sLowe

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Posts posted by sLowe


  1. Another good way to fix the timing of all this. I thought I would add this since it seems relevant. (I may use this project for something in the future)

    Although I'm curious why Vivado can't synthesize the /10 %10 procedure to something better. Maybe the real solution is to pipe the process and just introduce a couple clock cycles of lag.


  2. Hey Billel,

    Unfortunately looking the datasheet  of the AD here, it looks like it does not have a bi polar mode. However since your signal has a peak to peak value of 2, you can bias its ground to 1 V. So your sin wave signal should look like a sin wave going from 0 to 2V. Then in your logic you can subtract 1 V from all of your reading to receive negative values. 

    Since you are working with the basys you could also use the XADC core which has a bipolar mode if you are not attached to the PmodAD1. However you will again need to transform your input to have a peak to peak voltage of 1 V.

    - Sam


  3. Hi Josh,

    A good reference may be the DMA audio demo with the zybo located here https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start

    It will at least show you the I2S controller and the initialization sequence of the codec. You could use the SD card but it may be worth trying to load the sounds into the DDR on startup if there is enough space.

    If your project doesn't use the arm core, the guitar looper demo sets up a different codec but the only difference is in the start up i2C writes. Namely this project uses the I2S interface through HDL. That demo can be found here https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-looper-demo/start

    Good luck! Sounds like a fun addition to a pong game! After listening to all 33 sounds....... I have concluded my favorite blip is pongblipD#5

    https://www.freesound.org/people/NoiseCollector/packs/254/?page=1#sound

    - Sam

     


  4. Hi Sophia,

    I think the short answer to your question is yes, that is doable. However, if you want to use the BRAM IP provided by Xilinx, I don't think that you can have your PS writing values and have your PL reading them directly. You will probably have to read and write from PS alone. So when your PL logic needs to read a value, request it from the PS somehow and have the PS send the desired value via a FIFO buffer or a receive register in a custom IP. If you want to really get tricky you could probably throw a DMA controller in there if you are reading large chunks of data.

    Here is a guide to creating an axi custom IP core. This allows you to use the axi interface while writing your own logic in HDL.

    https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start

    Hope this helps,

    -Sam


  5. Hello,

    This board will connect to the nexys video. It was designed with the Zedboard in mind which uses the same FMC port as the video. For some more piece of mind you can look at the schematics and see that the FMC ports are of the same part and connection. (part  ASP-134603)

    https://reference.digilentinc.com/_media/reference/programmable-logic/zedboard/zedboard_sch.pdf

    https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexys_video_sch.pdf

    - Sam


  6. Yea I think there may have been a more clear way to do that math. Maybe I'll add a comment above that line. In the project I do the multiply before shifting right which avoids the two bit precision which would be a big problem. 

    Also in the project is the gross /10, &10 chain that calculates the decimal values but that will throw timing errors. I think what needs to be done is some sort of BCD conversion to evaluate those digits faster. Or spread the process over multiple clock cycles since the display doesn't need to be updated as fast as values are coming in.

    -Sam


  7. I think the best solution would be to make your own custom AXI IP with some registers that the processor can modify. Here is a guide

    https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start?redirect=1

    Another idea would to be to look at the FIFO IP and see if you can leverage the AXIS interface to your advantage.

    https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf

    https://www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf

    -Sam


  8. I would do your comparison in binary since you can use non floating point numbers. This will allow the tools to do a simple binary comparison which should be faster.

     I am pretty sure the timing error stems from the /10 %10 logic used to decipher the digits to send to the display. I didn't see the timing error as a huge issue since my eyes cant realize an error and nothing else is calculated off of those values.

     

    I think you are getting zeroes because you instantiate voltage as a reg, any reading you get divided by 4096 = 0. You either need to pull some verilog trickiness to allow these decimal numbers or do what I did and only shift right 10 (/1024)  and multiplying it by 250000 gets you your  voltage = (12-bit_ADC_code/4096)*100000. This gave me the voltage in microvolts

    Also your .5 sin wave should be biased at .5 V to start with. Your wave should still have a range of 0 to 1 with .5 being your virtual reference. I would expect that you would still see half of the wave(positive half) with this method though.

    -Sam


  9. They got changed when you programmed to the FPGA? Not when you regenerated the BSP?

    I don't know why that would happen. If the usleep gets called in the .c file within the BSP/libsrc/PmodOLEDrgb you should be able to make edits. They should stay as long as you don't regenerate the BSP. 

    The next step I would take would be to delete your BSP/Project then go into the files yourself in vivado-library\ip\Pmods\pmodOLEDrgb_v1_0\drivers\PmodOLEDrgb_v1_0\src and make the changes and save. You will then need to go back into vivado and update your IP. Rebuild the prject, then open sdk and create a new project and BSP. The changes should now be in your new BSP and will be included when you program your FPGA.

    Hope this works. I would try doing this instead of waiting for the applications team to get to this since for most of them it is Thanksgiving break. If you can branch and edit this gist with the changes, Id be happy to push it up to git for you!

    https://gist.github.com/SamKLowe/21087f1238e0f24f761a08aa24f75629

    -Sam


  10. Also I'm guessing you are getting that issue from not selecting channel 11 in the IP wizard under the channel sequencer tab. You need to make sure they are checked and under the basic tab you need to select Channel sequencer

     


  11. Hey,

    The quick fix to edit the BSP driver files is to just drag them into your project src along with your main. This will make sure that even if your BSP gets rebuilt, you will still have your changes. I've added this to our to do list and should be pushed up relatively soon.

    To make these projects work in both microblaze and zynq we usually use a custom delay function. For some reason this project didn't get it.

    #ifdef XPAR_MICROBLAZE_ID
    	#define ITERS_PER_USEC   (XPAR_CPU_CORE_CLOCK_FREQ_HZ / 1000000)
    #else
    	#define ITERS_PER_USEC     (XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ / 1000000)
    #endif
    
    void delay(int micros){
    	int i;
    
    #ifdef XPAR_MICROBLAZE_ID
    	for(i = 0; i < (ITERS_PER_USEC*micros); i++){
    			asm("");
    	}
    #else
    	usleep(micros);
    #endif
    }

    Thanks,

    Sam


  12. This error has something to do with having different versions of Vivado. It may be a couple things. Have you tried resetting your implementation run and rebuilding? 

    I forgot to actually add the github link to the wiki. I have now. It seems like it is not liking the simulation runs since I was using Vivado 2016.2 to generate the IPs. 

    I would first try right clicking on the IP's and choosing regenerate output products. If your IPs are locked, you may need to take note of your IP settings and delete and re instantiate these IPs with the same settings as your project earlier. 

    If you cant get this I can help you with getting a project going with your version of Vivado.

    -Sam

     


  13. Hey Fouad,

    The reason some of the VHDL is read only is because they belong to one of Xilinx's IPs. You can use the IP packager to edit any of the Digilent owned cores.

    Which IP block were you trying to edit? It makes sense to me to edit the dvi2rgb_0 core. You can do this by right clicking the core then select "edit in IP packager". You can then edit this VHDL and rebuild the IP.

    Ill keep an eye here in case I misunderstood the question.

    -Sam

     


  14. There is an alarms tab in the IP which may produce what you are looking for. 

    You can set what value you want for the OT alarms and then that produces a signal coming out of the IP.

    -Sam

     

     


  15. 1.) The real question is how to get the Pmod's data into microblaze. Which Pmod are you using? If it is one of digilents, there is a good chance we have a Pmod IP core that will make getting data easy in microblaze. The list can be found here. If you already have written some HDL to interface with the Pmod, you may need to follow this guide to create your own axi IP core that can transfer your data to microblaze.

    2.) Xilinx has this but it is pretty hidden. While in SDK you can go to system.mss in the BSP. Then you can click on the Ethernetlite documentation. This will take you to Xilinx's documentation of the sdk libraries associated with that IP. You can also import examples from system.mss

    -Sam


  16. This problem came from a chat between myself and @Vidar . His Macbook pro isnt recognizing an analog discovery 2. He is going to try another computer to see if his drivers will install correctly but it may be another problem. Hopefully the community and maybe @attila can chime in to help Vidar out. Here are the cliff notes of the chat.

     

    Well, the device seems to be dead.
    11:12 AM
    sLowe
    Which device?
    11:13 AM
    Vidar
    Analog Discovery 2

    Vidar

    I just received my Analog Discovery 2. I installed the WaveForms2, connected the device and nothing happens. No LEDs indicate that the unit is alive. I power the device with external 5V supply without any change. When starting up WaveForms 2015 no device is found. It seams as the Analog Discovery 2 unit is dead? What can be the reason? What shall I do?
    11:13 AM


    sLowe
    are you using linux?
    11:15 AM


    Vidar
    MacBook Pro
    11:15 AM

    sLowe
    so you plug your AD2 into your computer and nothing happens? I don't have too much experience with mac but there should be a device manager
    11:16 AM

    does it show up as anything?
    11:17 AM


    Vidar
    There is no LED's on the device that indicate live. I assume there should be some LED activity?
    11:18 AM

    Nothing shows up at the Device Manager
    11:18 AM


    sLowe
    No leds show up for me until the correct drivers install
    11:19 AM

    what version of OS do you have?
    11:20 AM


    Vidar
    10.11.6
    11:21 AM

    I assumed that there should be LED activity immediately when the unit is powered up? If the case is that the driver has to be running I can try another PC to see if it has something to do with my Mac and the driver.

    sLowe
    One thing it may be is that your computer power output settings may be restricting it. Using a USB hub could be worth a try
    11:24 AM

    also here is a pretty good thread
    11:24 AM


    Vidar
    I have tried that11:27 AM

    I think trying another computer could be helpful. My bet is that your drivers arent installing correctly
    11:27 AM


    Vidar
    Ok, thank you. I will try another PC.