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Everything posted by sLowe

  1. sLowe

    DDR3 Usage

    Hi Blueshark, This page may also be useful[]=ram2ddr This is the module that the looper demo that Jon referenced uses. (Hi Jon!) It may need some adjusting since its the arty but I'm not sure. -Sam
  2. sLowe

    Cmod A7 Clocking

    @etownsend Another thing to note is that the part is a no load so if you want to add the IC you have the option to put it on yourself. Although [email protected] has a more practical approach using a PLL to achieve 100MHz. I personally use the Xillinx Clocking Wizard. Although it's not as fun as [email protected]'s way.
  3. sLowe

    XADC demo

    Another good way to fix the timing of all this. I thought I would add this since it seems relevant. (I may use this project for something in the future) Although I'm curious why Vivado can't synthesize the /10 %10 procedure to something better. Maybe the real solution is to pipe the process and just introduce a couple clock cycles of lag.
  4. Hey Diya, Sorry if this is late, but it sounds like your jumper is not in the correct position? In section 3.2 of the Reference Manual here, it shows you what to set it as. The manual also references a project that can take you through the process. That can be downloaded on the resource center page or here. base system design -Sam
  5. sLowe

    XADC demo

    Just as a follow up I made a BCD controller out to ten digits that can be found here.
  6. sLowe

    Zybo + PMOD +C

    Hey Oscar, This is very doable and actually Digilent made a GPIO Pmod IP for you. If you follow the guide below, you can use the GPIO IP to achieve the behavior you want. Instead of DigitalWrite, you just call GPIO_setPin(Instance ptr, pin, value) You could also just use your own xilinx GPIO IP and use its functions. -Sam
  7. Hey Billel, Unfortunately looking the datasheet of the AD here, it looks like it does not have a bi polar mode. However since your signal has a peak to peak value of 2, you can bias its ground to 1 V. So your sin wave signal should look like a sin wave going from 0 to 2V. Then in your logic you can subtract 1 V from all of your reading to receive negative values. Since you are working with the basys you could also use the XADC core which has a bipolar mode if you are not attached to the PmodAD1. However you will again need to transform your input to have a peak to peak voltage of 1
  8. You probably just left it out but looking at your procedure, after you add the bitstream from HW Export, you should add the elf file from your hello world project before creating your .bin. -Sam
  9. Hi Josh, A good reference may be the DMA audio demo with the zybo located here It will at least show you the I2S controller and the initialization sequence of the codec. You could use the SD card but it may be worth trying to load the sounds into the DDR on startup if there is enough space. If your project doesn't use the arm core, the guitar looper demo sets up a different codec but the only difference is in the start up i2C writes. Namely this project uses the I2S interface through
  10. Hi Sophia, I think the short answer to your question is yes, that is doable. However, if you want to use the BRAM IP provided by Xilinx, I don't think that you can have your PS writing values and have your PL reading them directly. You will probably have to read and write from PS alone. So when your PL logic needs to read a value, request it from the PS somehow and have the PS send the desired value via a FIFO buffer or a receive register in a custom IP. If you want to really get tricky you could probably throw a DMA controller in there if you are reading large chunks of data. Here i
  11. Hello, This board will connect to the nexys video. It was designed with the Zedboard in mind which uses the same FMC port as the video. For some more piece of mind you can look at the schematics and see that the FMC ports are of the same part and connection. (part ASP-134603) - Sam
  12. Hello, Which Digilent board are you using? I think this error is on the board file side instead of the PmodIP. -Sam
  13. sLowe

    XADC demo

    Yea I think there may have been a more clear way to do that math. Maybe I'll add a comment above that line. In the project I do the multiply before shifting right which avoids the two bit precision which would be a big problem. Also in the project is the gross /10, &10 chain that calculates the decimal values but that will throw timing errors. I think what needs to be done is some sort of BCD conversion to evaluate those digits faster. Or spread the process over multiple clock cycles since the display doesn't need to be updated as fast as values are coming in. -Sam
  14. I think the best solution would be to make your own custom AXI IP with some registers that the processor can modify. Here is a guide Another idea would to be to look at the FIFO IP and see if you can leverage the AXIS interface to your advantage.
  15. I believe these delays are just for simulation purposes. The warnings are basically saying you haven't specified your input and output delays to the real world so a system that works in theory may not work on the board. I have successfully ignored them in the past if I am wrong about that. -Sam
  16. sLowe

    XADC demo

    I would do your comparison in binary since you can use non floating point numbers. This will allow the tools to do a simple binary comparison which should be faster. I am pretty sure the timing error stems from the /10 %10 logic used to decipher the digits to send to the display. I didn't see the timing error as a huge issue since my eyes cant realize an error and nothing else is calculated off of those values. I think you are getting zeroes because you instantiate voltage as a reg, any reading you get divided by 4096 = 0. You either need to pull some verilog trickiness to al
  17. They got changed when you programmed to the FPGA? Not when you regenerated the BSP? I don't know why that would happen. If the usleep gets called in the .c file within the BSP/libsrc/PmodOLEDrgb you should be able to make edits. They should stay as long as you don't regenerate the BSP. The next step I would take would be to delete your BSP/Project then go into the files yourself in vivado-library\ip\Pmods\pmodOLEDrgb_v1_0\drivers\PmodOLEDrgb_v1_0\src and make the changes and save. You will then need to go back into vivado and update your IP. Rebuild the prject, then open sdk and cre
  18. sLowe

    XADC demo

    Also I'm guessing you are getting that issue from not selecting channel 11 in the IP wizard under the channel sequencer tab. You need to make sure they are checked and under the basic tab you need to select Channel sequencer
  19. Hey, The quick fix to edit the BSP driver files is to just drag them into your project src along with your main. This will make sure that even if your BSP gets rebuilt, you will still have your changes. I've added this to our to do list and should be pushed up relatively soon. To make these projects work in both microblaze and zynq we usually use a custom delay function. For some reason this project didn't get it. #ifdef XPAR_MICROBLAZE_ID #define ITERS_PER_USEC (XPAR_CPU_CORE_CLOCK_FREQ_HZ / 1000000) #else #define ITERS_PER_USEC (XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ / 10
  20. sLowe

    XADC demo

    This error has something to do with having different versions of Vivado. It may be a couple things. Have you tried resetting your implementation run and rebuilding? I forgot to actually add the github link to the wiki. I have now. It seems like it is not liking the simulation runs since I was using Vivado 2016.2 to generate the IPs. I would first try right clicking on the IP's and choosing regenerate output products. If your IPs are locked, you may need to take note of your IP settings and delete and re instantiate these IPs with the same settings as your project earlier. If
  21. Hey Fouad, The reason some of the VHDL is read only is because they belong to one of Xilinx's IPs. You can use the IP packager to edit any of the Digilent owned cores. Which IP block were you trying to edit? It makes sense to me to edit the dvi2rgb_0 core. You can do this by right clicking the core then select "edit in IP packager". You can then edit this VHDL and rebuild the IP. Ill keep an eye here in case I misunderstood the question. -Sam
  22. sLowe

    XADC demo

    Hey Manas, Looking at the register space in this guide on page 17 I don't see a way to set up an alarm inside of the ip. You may have to externally read both values and subtract it on your own. -Sam
  23. sLowe

    XADC demo

    There is an alarms tab in the IP which may produce what you are looking for. You can set what value you want for the OT alarms and then that produces a signal coming out of the IP. -Sam
  24. sLowe

    Nexys4 DDR ethernet

    1.) The real question is how to get the Pmod's data into microblaze. Which Pmod are you using? If it is one of digilents, there is a good chance we have a Pmod IP core that will make getting data easy in microblaze. The list can be found here. If you already have written some HDL to interface with the Pmod, you may need to follow this guide to create your own axi IP core that can transfer your data to microblaze. 2.) Xilinx has this but it is pretty hidden. While in SDK you can go to system.mss in the BSP. Then you can click on the Ethernetlite documentation. This will take you to Xilinx'
  25. This problem came from a chat between myself and @Vidar . His Macbook pro isnt recognizing an analog discovery 2. He is going to try another computer to see if his drivers will install correctly but it may be another problem. Hopefully the community and maybe @attila can chime in to help Vidar out. Here are the cliff notes of the chat. Well, the device seems to be dead. 11:12 AM sLowe Which device? 11:13 AM Vidar Analog Discovery 2 Vidar I just received my Analog Discovery 2. I installed the WaveForms2, connected the device and nothing happens. No LEDs indicat