sLowe

Digilent Staff
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sLowe last won the day on December 29 2016

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About sLowe

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  1. Cmod A7 Clocking

    @etownsend Another thing to note is that the part is a no load so if you want to add the IC you have the option to put it on yourself. Although D@n has a more practical approach using a PLL to achieve 100MHz. I personally use the Xillinx Clocking Wizard. Although it's not as fun as D@n's way.
  2. XADC demo

    Another good way to fix the timing of all this. I thought I would add this since it seems relevant. (I may use this project for something in the future) Although I'm curious why Vivado can't synthesize the /10 %10 procedure to something better. Maybe the real solution is to pipe the process and just introduce a couple clock cycles of lag.
  3. Program Zybo board QSPI FLASH with .mcs file

    Hey Diya, Sorry if this is late, but it sounds like your jumper is not in the correct position? In section 3.2 of the Reference Manual here, it shows you what to set it as. The manual also references a project that can take you through the process. That can be downloaded on the resource center page or here. base system design -Sam
  4. XADC demo

    Just as a follow up I made a BCD controller out to ten digits that can be found here. https://gist.github.com/SamKLowe/b126dd6f2e77bb31e3235c6e588c5c0a
  5. Zybo + PMOD +C

    Hey Oscar, This is very doable and actually Digilent made a GPIO Pmod IP for you. If you follow the guide below, you can use the GPIO IP to achieve the behavior you want. Instead of DigitalWrite, you just call GPIO_setPin(Instance ptr, pin, value) https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start You could also just use your own xilinx GPIO IP and use its functions. -Sam
  6. How to get a negative value with PMODAD1

    Hey Billel, Unfortunately looking the datasheet of the AD here, it looks like it does not have a bi polar mode. However since your signal has a peak to peak value of 2, you can bias its ground to 1 V. So your sin wave signal should look like a sin wave going from 0 to 2V. Then in your logic you can subtract 1 V from all of your reading to receive negative values. Since you are working with the basys you could also use the XADC core which has a bipolar mode if you are not attached to the PmodAD1. However you will again need to transform your input to have a peak to peak voltage of 1 V. - Sam
  7. PYNQ-Z1 Standalone Bootloader Generation (QSPI/SD)

    You probably just left it out but looking at your procedure, after you add the bitstream from HW Export, you should add the elf file from your hello world project before creating your .bin. -Sam
  8. Getting Started w/ Audio on Zybo

    Hi Josh, A good reference may be the DMA audio demo with the zybo located here https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start. It will at least show you the I2S controller and the initialization sequence of the codec. You could use the SD card but it may be worth trying to load the sounds into the DDR on startup if there is enough space. If your project doesn't use the arm core, the guitar looper demo sets up a different codec but the only difference is in the start up i2C writes. Namely this project uses the I2S interface through HDL. That demo can be found here https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-looper-demo/start Good luck! Sounds like a fun addition to a pong game! After listening to all 33 sounds....... I have concluded my favorite blip is pongblipD#5 https://www.freesound.org/people/NoiseCollector/packs/254/?page=1#sound - Sam
  9. Can I program zybo in PS and PL?

    Hi Sophia, I think the short answer to your question is yes, that is doable. However, if you want to use the BRAM IP provided by Xilinx, I don't think that you can have your PS writing values and have your PL reading them directly. You will probably have to read and write from PS alone. So when your PL logic needs to read a value, request it from the PS somehow and have the PS send the desired value via a FIFO buffer or a receive register in a custom IP. If you want to really get tricky you could probably throw a DMA controller in there if you are reading large chunks of data. Here is a guide to creating an axi custom IP core. This allows you to use the axi interface while writing your own logic in HDL. https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start Hope this helps, -Sam
  10. FMC-CE: Basic Input/Output Expansion Board

    Hello, This board will connect to the nexys video. It was designed with the Zedboard in mind which uses the same FMC port as the video. For some more piece of mind you can look at the schematics and see that the FMC ports are of the same part and connection. (part ASP-134603) https://reference.digilentinc.com/_media/reference/programmable-logic/zedboard/zedboard_sch.pdf https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexys_video_sch.pdf - Sam
  11. ERROR with PmodOLED IP and Vivado Board File

    Hello, Which Digilent board are you using? I think this error is on the board file side instead of the PmodIP. -Sam
  12. XADC demo

    Yea I think there may have been a more clear way to do that math. Maybe I'll add a comment above that line. In the project I do the multiply before shifting right which avoids the two bit precision which would be a big problem. Also in the project is the gross /10, &10 chain that calculates the decimal values but that will throw timing errors. I think what needs to be done is some sort of BCD conversion to evaluate those digits faster. Or spread the process over multiple clock cycles since the display doesn't need to be updated as fast as values are coming in. -Sam
  13. Transfer of data from PS to PL in Zynq 702 SoC

    I think the best solution would be to make your own custom AXI IP with some registers that the processor can modify. Here is a guide https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start?redirect=1 Another idea would to be to look at the FIFO IP and see if you can leverage the AXIS interface to your advantage. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf https://www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf -Sam
  14. I believe these delays are just for simulation purposes. The warnings are basically saying you haven't specified your input and output delays to the real world so a system that works in theory may not work on the board. I have successfully ignored them in the past if I am wrong about that. -Sam
  15. XADC demo

    I would do your comparison in binary since you can use non floating point numbers. This will allow the tools to do a simple binary comparison which should be faster. I am pretty sure the timing error stems from the /10 %10 logic used to decipher the digits to send to the display. I didn't see the timing error as a huge issue since my eyes cant realize an error and nothing else is calculated off of those values. I think you are getting zeroes because you instantiate voltage as a reg, any reading you get divided by 4096 = 0. You either need to pull some verilog trickiness to allow these decimal numbers or do what I did and only shift right 10 (/1024) and multiplying it by 250000 gets you your voltage = (12-bit_ADC_code/4096)*100000. This gave me the voltage in microvolts Also your .5 sin wave should be biased at .5 V to start with. Your wave should still have a range of 0 to 1 with .5 being your virtual reference. I would expect that you would still see half of the wave(positive half) with this method though. -Sam