PhDev

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PhDev last won the day on September 22 2018

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  1. Hi @ntm I think you should have a look at this example: In the example I use the new Instant SoC / Risc V tool. I now use it instead of microblaze when I do smaller projects like the one you describes. The output is VHDL however there is a also verilog wrapper generated.
  2. PhDev

    spi with accelerometer

    Hi @sseroussi I did a project in the Project Vault. That shows how to use the accelerometers on the Nexys 4 board using Instant SoC. That system compiles C++ code directly to a CPU ( RISC-V ) and SPI and other peripherals. It is very easy to use.
  3. I tried the new Instant SoC from FPGA Cores on my Nexys 4 DDR (Nexys A7) board. Instant SoC is a C++ compiler that compiles C++ directly to a RISC-V processor and peripherals. The result is one vhdl file that I synthesized with Vivado. The only file I needed to add was the constraints file to map the signals to pins. The code implements a simple inclinometer. This is a description of what the code does: Sleeps 100 ms Read accelerations from the on board accelerometer using SPI Calculates angles using floating point math (atan, sqrt) Removes the zero offset that is reset using the center button. Print angles with one decimal point on UART Set the angles on 7 segment display Calculates an effect on the 16-leds. A led is “rolling” to the direction the board is leaning. Repeat A lot of the code was taken from Instant SoC class lib doc. The "hardware section", first in the main file defines the IO etc. In this case I created the following objects: ... int main(void) { //% hw_begin FC_IO_Clk Clk(100); FC_IO_Out LED(16); FC_IO_SPI accel(1000000,0,8); FC_IO_UART_TX uart_tx(115200,32); FC_IO_SegmentDisplay s7(8,8,0); FC_IO_In button_center; FC_System_Timer timer; //% hw_end uart_tx << "\r\nInclinometer demo using Nexys\r\n"; ... When compiling this it resulted in a VHDL file with the following port signals: ... entity nexys is port( Clk : in std_logic; LED : out std_logic_vector(15 downto 0); accel_SCLK : out std_logic; accel_MOSI : out std_logic; accel_MISO : in std_logic; accel_SSn : out std_logic; uart_tx : out std_logic; s7_seg : out std_logic_vector(7 downto 0); s7_sel : out std_logic_vector(7 downto 0); button_center : in std_logic ); end entity; architecture IMPL of nexys is ... And if you prefer Verilog there is also a Verilog header file generated: ... module nexys( input Clk, output [15:0] LED, output accel_SCLK, output accel_MOSI, input accel_MISO, output accel_SSn, output uart_tx, output [7:0] s7_seg, output [7:0] s7_sel, input button_center ); endmodule ... The system is free to download. I have attached the bit file (zipped) so it is possible to see what the C++ does. nexys.cpp nexys.xdc nexys_bit.zip
  4. @yildizabdullah spi_clk is an input to STARTUPE2 and can not have a loc constraint. It will automatically be routed to E9.
  5. @D@n Yes I think they work great. Very easy to use. I have mostly been using FC1002 with TCP. I have also used FC1003 in a project where UDP (broadcast) was a better choice. I hope they release a FC1004 with RMII: (Both UDP and TCP) DHCP or fix IP works as expected. The remote programmer also works very good. I think it is faster and easier than using XIlinx programming tools. The logic analyzer is also very useful for debugging the system without using the jtag. Only bad thing is that I sometimes need larger sample buffers. I also miss some documentation, however I think I have figured it out most of it now. I really like the AXI-stream. Xilinx has very good components supporting this like clock domain crossing, FIFO, Filters etc.
  6. @Aamirnagra I think you could take a look at these Ethernet cores. There are cores for Spartan 6 that you can download for free. These cores contains all you need to communicate with a PC or Linux like TCP, UDP, Ping etc.
  7. Hi @sieg70 You can use the STARTUPE2 primitive to access E9. STARTUPE2_i : STARTUPE2 port map ( CFGCLK => open, -- 1-bit output: Configuration main clock output CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => open, -- 1-bit output: PROGRAM request to fabric output CLK => '0', -- 1-bit input: User start-up clock input GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name) KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) PACK => '0', -- 1-bit input: PROGRAM acknowledge input USRCCLKO => SPI_Clk, -- 1-bit input: User CCLK input USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input USRDONEO => '0', -- 1-bit input: User DONE pin output control USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output ); With this SPI_Clk goes to E9.
  8. Hi @raultricking I think you should look at these FPGA Ethernet Cores. The cores includes everything you need for Ethernet like TCP/IP, UDP, DHCP and so on. The cores also have remote boot flash programming and an internal logic analyzer. There is an example using your board. You will be up and running in minutes 🙂
  9. Hi @bklopp, I can recommend you to look at fpga-cores.com if you do signal processing. With this core you don't need any processor etc. You only stream the data and the core do all Ethernet stuff like TCP/IP. It is then very simple to use from Matlab, Python or what ever you prefer. With their logic analyzer you can view the signal as analog, so you can easily look at the signal during all steps. All cores and software can you download for free. Cheers
  10. PhDev

    Arty A7 and Arty S7

    Hi, the main difference (in my point of view) is that Arty S7 doesn't have any Ethernet connection. (Why?) When I develop signal processing stuff etc in Matlab and test them on hardware I use TCP/IP to AXI4 streams, so for me S7 is not usable. Cheers
  11. PhDev

    Protocol Development

    @Middy Yes you need to write a simple process that writes data to the AXI stream however you don't need any additional memory. It is in the IP. AXI stream is a very simple protocol. Basically the transfer takes place when both Ready and Valid is '1'. I can really recommend everyone to look at it. Xilinx has a lot of components that support this protocol like FIFOs, FIR filters, clock domain borders etc. If you use UDP the only thing you have to do is to decide a packet length since UDP is packet oriented. When adding the last byte in the packet you set TxLast to '1'. When you use UDP server you need to write something from the PC so the FPGA(server) knows the PCs (client) address. In your case I think using the TCP could be easier. Then you don't need to set packets length etc you only add data to the stream and the core do everything else. The TCP is also taking care of re-transmitting etc.
  12. PhDev

    Protocol Development

    Hi Middy, I have done similar tasks and then I have used the cores from fpga-cores.com/. I have used it on Arty A7 board and it works very well. There is a built in logic analyzer in the core so you can watch the internal signals and you can also stream the data to the TCP or UDP port. You will be up and running in a couple of minutes :-) And everything is free to use... You have to look at the AXI4 Stream protocol to interface the TCP or UDP port.
  13. PhDev

    Arty and Ethernet

    Hi Fields, the easiest way (I think...) is to use one of the cores from FPGA Cores. There is also a tutorial using Arty. You can find the tutorial here.
  14. PhDev

    Ethernet on Arty Z7

    Thanks for reply. What project? The problem is using mio on zynq, Arty z7.
  15. PhDev

    Ethernet on Arty Z7

    Hi Is it possible to use the Ethernet phy on Arty Z7 direct from the programmable logic? I want to use my own MAC. How do I do that? Cheers