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  1. I have been using the Ethernet cores from for a couple of years now and they work without problem. They contains all you need to connect your FPGA to Ethernet. Really simple to use. No processor needed. They are free to download. There is a tutorial Nexus board here. It is only possible to use these cores when the phy is connected to PL on the Zynq devices.
  2. Hi, I think you should have a look at Instant SoC. It is a very simple way to solve what you want to do. It compiles C/C++ to vhdl and have classes for UARTs etc. You can do division, truncation and so on. It is free to download and use.
  3. What do you mean with Since you are using a FC1002 Ethernet core the TCP packet data will be streamed out to logic with an AXI stream. This stream is used by your logic. The AXI stream signals are TCP0_TxData, TCP0_TxValid, TCP0_TxReady for transmit data and TCP0_RxData, TCP0_RxValid, TCP0_RxReady for receive data
  4. PhDev

    Arty S7 I2C example

    Hi Erick. If you like C++ I can recommend you to look at Instant-SoC. It generates the hardware needed based on your C++ code. I have not used it with Arty S7 board however I have used it a lot with Arty A7. Here you can find an example using the I2C class.
  5. Hi, I did an example using Instant SoC and it is in the project vault. Maybe that can help.
  6. @Jay D I recommend you to have a look at this tutorial. This core do all Ethernet protocols (ARP, DHCP, UDP, TCP, ICMP etc) that you need without use of any operating system or extra memory. I use it all the time and have not found any problems. You can download and use it for free. The remote programmer also works great. If you do any signal processing like I do there is also a remote logic analyzer that works very good as an internal oscilloscope.
  7. Hi @ntm I think you should have a look at this example: In the example I use the new Instant SoC / Risc V tool. I now use it instead of microblaze when I do smaller projects like the one you describes. The output is VHDL however there is a also verilog wrapper generated.
  8. PhDev

    spi with accelerometer

    Hi @sseroussi I did a project in the Project Vault. That shows how to use the accelerometers on the Nexys 4 board using Instant SoC. That system compiles C++ code directly to a CPU ( RISC-V ) and SPI and other peripherals. It is very easy to use.
  9. I tried the new Instant SoC from FPGA Cores on my Nexys 4 DDR (Nexys A7) board. Instant SoC is a C++ compiler that compiles C++ directly to a RISC-V processor and peripherals. The result is one vhdl file that I synthesized with Vivado. The only file I needed to add was the constraints file to map the signals to pins. The code implements a simple inclinometer. This is a description of what the code does: Sleeps 100 ms Read accelerations from the on board accelerometer using SPI Calculates angles using floating point math (atan, sqrt) Removes the zero offset that is res
  10. @yildizabdullah spi_clk is an input to STARTUPE2 and can not have a loc constraint. It will automatically be routed to E9.
  11. @[email protected] Yes I think they work great. Very easy to use. I have mostly been using FC1002 with TCP. I have also used FC1003 in a project where UDP (broadcast) was a better choice. I hope they release a FC1004 with RMII: (Both UDP and TCP) DHCP or fix IP works as expected. The remote programmer also works very good. I think it is faster and easier than using XIlinx programming tools. The logic analyzer is also very useful for debugging the system without using the jtag. Only bad thing is that I sometimes need larger sample buffers. I also miss some documentation, however I think I
  12. @Aamirnagra I think you could take a look at these Ethernet cores. There are cores for Spartan 6 that you can download for free. These cores contains all you need to communicate with a PC or Linux like TCP, UDP, Ping etc.
  13. Hi @sieg70 You can use the STARTUPE2 primitive to access E9. STARTUPE2_i : STARTUPE2 port map ( CFGCLK => open, -- 1-bit output: Configuration main clock output CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => open, -- 1-bit output: PROGRAM request to fabric output CLK => '0', -- 1-bit input: User start-up clock input GSR => '0', -- 1-b
  14. Hi @raultricking I think you should look at these FPGA Ethernet Cores. The cores includes everything you need for Ethernet like TCP/IP, UDP, DHCP and so on. The cores also have remote boot flash programming and an internal logic analyzer. There is an example using your board. You will be up and running in minutes 🙂
  15. Hi @bklopp, I can recommend you to look at if you do signal processing. With this core you don't need any processor etc. You only stream the data and the core do all Ethernet stuff like TCP/IP. It is then very simple to use from Matlab, Python or what ever you prefer. With their logic analyzer you can view the signal as analog, so you can easily look at the signal during all steps. All cores and software can you download for free. Cheers