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About deppenkaiser

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  1. @morsucci, uio-interrupt is working. I made an error in my pointer arithmetic.
  2. @deppenkaiser, you don't Need an other board, because uio-interrupt is working.
  3. @deppenkaiser, your macro to Access the Memory is wrong, if you would use the right macro, then your Offset calculation would work. @sbobrowicz: I found the error in my Offset calculation, thats could be also the reason for my uio issue! :-) I will tell you the results.
  4. Hello @sbobrowicz, 1. I got "". 2. I fixed the incomplete archive with "". 3. I fixed the Vivado build Errors. 4. I created a Linux "Hello world"-App with SDK. 5. I created and configure a new petalinux project with the get-hw-description Option. 6. I build the petalinux image. 7. I saw no uio devices. 8. I added one uio device for the "axi_gpio_sw" device (with Interrupt). 9. I build a new petalinux image. 10. I saw one uio device with registered Interrupts in /proc/interrupts 11. I Chang
  5. Hello, you know, that i try to use uio. And i still got no result. Therefor i try the next Vivado 2018.1 with the still not delivered petalinux. I created a new Project in Vivado 2018.1 and i tried to choose the Arty-Z7-20 board. But i can't select it; before i did it, i copied the digilent board files into the Xilinx Directory. When do you provide the new board files for Vivado 2018.1; i Need the Arty-Z7-20 :-) Thank you...
  6. Hello, finally i was able to make a petalinux build with the BSP 2017.4 - so far, so good. Then i find out, which uio device is connected with the Arty-Z7-20 Buttons and switches. Both - the Buttons and also the Switches - are connected to one GPIO-IP-Core (Dual-Channel, all inputs). One AXI-GPIO has one base address and a dual channel GPIO has even only one base address. So the only way to address both channels is to use the base address offset for channel one and for channel two, isn't it? If i read channel one - which is assigned to the Buttons - then i can read the Buttons.
  7. @morsucci, i think that i have two ways to get a petalinux configuration. The first way is to extract the configuration from the BSP and the second way is to get it from the HDF (new configuration but suited to the design). You know, that i still have the uio issue. So the reason for the things i did - even this thread - is to get the "digilent" configuration from BSP which is able to support uio Interrupts; because you told me that they exist and work. In the Xilinx Forum i got some help but it won't help. The english Queen would say "I'am not amused." I have invested a lo
  8. It seems that some "digilent-apps" are not available, isn't it? Summary: 3 tasks failed: /home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libuio/ /home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libgpio/ /home/czymic/projects/2017.4/Arty-Z7-20/project-spec/meta-user/recipes-apps/digilent-apps/libpwm/ Summary: There were 6 ERROR messages shown, returning a non-zero exit code. ERROR: Failed to build project Do i need the apps and what
  9. Hello, i have some errors while building the 2017.4 BSP based petalinux image. [email protected]:~/projects/2017.4/Arty-Z7-20$ petalinux-build [INFO] building project [INFO] sourcing bitbake INFO: bitbake petalinux-user-image Parsing recipes: 100% |##########################################| Time: 0:01:30 Parsing of 2473 .bb files complete (0 cached, 2473 parsed). 3266 targets, 226 skipped, 0 masked, 0 errors. NOTE: Resolving any missing task queue dependencies Initialising tasks: 100% |#######################################| Time: 0:00:06 Checking sstate mirror object a
  10. @jpeyron, FYI: The Vivado-Build still has some Errors which i have fixed. Now, I try to build the petalinux image which is derived from the given bsp. I will tell you the results later.
  11. @jpeyron, sorry, where is the download Content? I see only this: And here you can see my repo Folder: regards deppenkaiser
  12. @deppenkaiser, please look here:
  13. Hello, i was very happy, that i got the new 2017.4 Vivado design, but my happyness ends after five minutes. I have build Errors, can you please tell me what i have to do? Here is the screenshot: Thank you...
  14. @jpeyron, is the zedboard a product from digilent? Who is "AVNET"? You know my uio issue, i asked the same question on the Xilinx Forum. The answers i got say, that my Code is looking good, but there is one difference that i should check. I ask them what board they are using, and one of them told me, that he uses a zedboard. From my Point of view - at this Moment - the zedboard is the only board which Supports the needed funtionality. It is surely not the same if i use your BSP or if i use "petalinux-create" to create a defaults based configuration. But it can not be u