deppenkaiser

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  1. Arty-Z7-20-base-linux

    Hello, i used the "Arty-Z7-20-base-linux"-project with Vivado 2017.2, first i copied the board files to my new installed vivado 2017.2 Installation and then i run the "create_project.tcl" script. So far so good. After that i have tried to create a hdl-wrapper, because i liked to generate a bitstream. Vivado has got the following error: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'Arty_Z7_20.bd' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: Arty_Z7_20_PWM_0_0 Arty_Z7_20_axi_dynclk_0_0 Arty_Z7_20_dvi2rgb_0_0 Arty_Z7_20_rgb2dvi_0_0 I followed the instruction and got: report_ip_status Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 | Date : Mon Dec 11 10:17:31 2017 | Host : IP415 running 64-bit Service Pack 1 (build 7601) | Command : report_ip_status ------------------------------------------------------------------------------------ IP Status Summary 1. Project IP Status -------------------- Your project uses 31 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. More information on the Xilinx versioning policy is available at www.xilinx.com. Project IP Instances +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | | | | | Log | | Version | | License | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_PWM_0_0 | IP definition not found | Add IP definition to catalog | Change | PWM | 2.0 | N/A | Included | xc7z020clg400-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 5) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_dynclk_0_0 | IP definition not found | Add IP definition to catalog | Change | axi_dynclk | 1.0 | N/A | Included | xc7z020clg400-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 3) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_gpio_0_0 | Up-to-date | No changes required | *(1) | AXI GPIO | 2.0 | 2.0 (Rev. 15) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 15) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_gpio_hdmi_0 | Up-to-date | No changes required | *(2) | AXI GPIO | 2.0 | 2.0 (Rev. 15) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 15) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_gpio_led_0 | Up-to-date | No changes required | *(3) | AXI GPIO | 2.0 | 2.0 (Rev. 15) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 15) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_gpio_shield_1_0 | Up-to-date | No changes required | *(4) | AXI GPIO | 2.0 | 2.0 (Rev. 15) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 15) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_gpio_sw_0 | Up-to-date | No changes required | *(5) | AXI GPIO | 2.0 | 2.0 (Rev. 15) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 15) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_mem_intercon_0 | Up-to-date | No changes required | *(6) | AXI Interconnect | 2.1 | 2.1 (Rev. 14) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 14) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_vdma_0_1 | Up-to-date | No changes required | *(7) | AXI Video Direct | 6.3 | 6.3 (Rev. 1) | Included | xc7z020clg400-1 | | | | | | Memory Access | (Rev. | | | | | | | | | | 1) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axi_vdma_1_0 | Up-to-date | No changes required | *(8) | AXI Video Direct | 6.3 | 6.3 (Rev. 1) | Included | xc7z020clg400-1 | | | | | | Memory Access | (Rev. | | | | | | | | | | 1) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axis_subset_converter_0_0 | Up-to-date | No changes required | *(9) | AXI4-Stream Subset | 1.1 | 1.1 (Rev. 13) | Included | xc7z020clg400-1 | | | | | | Converter | (Rev. | | | | | | | | | | 13) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_axis_subset_converter_1_0 | Up-to-date | No changes required | *(10) | AXI4-Stream Subset | 1.1 | 1.1 (Rev. 13) | Included | xc7z020clg400-1 | | | | | | Converter | (Rev. | | | | | | | | | | 13) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_clk_wiz_0_0 | Up-to-date | No changes required | *(11) | Clocking Wizard | 5.4 | 5.4 (Rev. 1) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 1) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_dvi2rgb_0_0 | IP definition not found | Add IP definition to catalog | Change | dvi2rgb | 1.7 | N/A | Included | xc7z020clg400-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_proc_sys_reset_0_0 | Up-to-date | No changes required | *(12) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z020clg400-1 | | | | | | Reset | (Rev. | | | | | | | | | | 11) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_proc_sys_reset_0_1 | Up-to-date | No changes required | *(13) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z020clg400-1 | | | | | | Reset | (Rev. | | | | | | | | | | 11) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_proc_sys_reset_0_2 | Up-to-date | No changes required | *(14) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z020clg400-1 | | | | | | Reset | (Rev. | | | | | | | | | | 11) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_proc_sys_reset_0_3 | Up-to-date | No changes required | *(15) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z020clg400-1 | | | | | | Reset | (Rev. | | | | | | | | | | 11) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_processing_system7_0_0 | Up-to-date | No changes required | *(16) | ZYNQ7 Processing | 5.5 | 5.5 (Rev. 5) | Included | xc7z020clg400-1 | | | | | | System | (Rev. | | | | | | | | | | 5) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_processing_system7_0_axi_periph_0 | Up-to-date | No changes required | *(17) | AXI Interconnect | 2.1 | 2.1 (Rev. 14) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 14) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_rgb2dvi_0_0 | IP definition not found | Add IP definition to catalog | Change | rgb2dvi | 1.3 | N/A | Included | xc7z020clg400-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_rst_processing_system7_0_100M_0 | Up-to-date | No changes required | *(18) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z020clg400-1 | | | | | | Reset | (Rev. | | | | | | | | | | 11) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_rst_processing_system7_0_142M_0 | Up-to-date | No changes required | *(19) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z020clg400-1 | | | | | | Reset | (Rev. | | | | | | | | | | 11) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_v_axi4s_vid_out_0_0 | Up-to-date | No changes required | *(20) | AXI4-Stream to | 4.0 | 4.0 (Rev. 6) | Included | xc7z020clg400-1 | | | | | | Video Out | (Rev. | | | | | | | | | | 6) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_v_tc_0_0 | Up-to-date | No changes required | *(21) | Video Timing | 6.1 | 6.1 (Rev. 10) | Included | xc7z020clg400-1 | | | | | | Controller | (Rev. | | | | | | | | | | 10) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_v_tc_1_0 | Up-to-date | No changes required | *(22) | Video Timing | 6.1 | 6.1 (Rev. 10) | Included | xc7z020clg400-1 | | | | | | Controller | (Rev. | | | | | | | | | | 10) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_v_vid_in_axi4s_0_0 | Up-to-date | No changes required | *(23) | Video In to | 4.0 | 4.0 (Rev. 6) | Included | xc7z020clg400-1 | | | | | | AXI4-Stream | (Rev. | | | | | | | | | | 6) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_xadc_wiz_0_0 | Up-to-date | No changes required | *(24) | XADC Wizard | 3.3 | 3.3 (Rev. 3) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 3) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_xlconcat_0_0 | Up-to-date | No changes required | *(25) | Concat | 2.1 | 2.1 (Rev. 1) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 1) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_xlconcat_1_0 | Up-to-date | No changes required | *(26) | Concat | 2.1 | 2.1 (Rev. 1) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 1) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ | Arty_Z7_20_xlconstant_0_0 | Up-to-date | No changes required | *(27) | Constant | 1.1 | 1.1 (Rev. 3) | Included | xc7z020clg400-1 | | | | | | | (Rev. | | | | | | | | | | 3) | | | | +----------------------------------------------+-------------------------+------------------------------+-----------+--------------------+---------+---------------+------------+----------------------+ *(1) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt *(2) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt *(3) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt *(4) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt *(5) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_gpio_v2_0/doc/axi_gpio_v2_0_changelog.txt *(6) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt *(7) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt *(8) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt *(9) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axis_subset_converter_v1_1/doc/axis_subset_converter_v1_1_changelog.txt *(10) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axis_subset_converter_v1_1/doc/axis_subset_converter_v1_1_changelog.txt *(11) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/clk_wiz_v5_4/doc/clk_wiz_v5_4_changelog.txt *(12) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(13) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(14) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(15) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(16) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/processing_system7_v5_5/doc/processing_system7_v5_5_changelog.txt *(17) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt *(18) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(19) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(20) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_axi4s_vid_out_v4_0/doc/v_axi4s_vid_out_v4_0_changelog.txt *(21) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_tc_v6_1/doc/v_tc_v6_1_changelog.txt *(22) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_tc_v6_1/doc/v_tc_v6_1_changelog.txt *(23) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/v_vid_in_axi4s_v4_0/doc/v_vid_in_axi4s_v4_0_changelog.txt *(24) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xadc_wiz_v3_3/doc/xadc_wiz_v3_3_changelog.txt *(25) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt *(26) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt *(27) c:/Xilinx/Vivado/2017.2/data/ip/xilinx/xlconstant_v1_1/doc/xlconstant_v1_1_changelog.txt As you can see, the reason is: "IP definition not found" for the listed ip-cores (see error message). Can you tell me, what i should do? What is a "Petalinux-Arty-Z7-20-2017.2-2.bsp" file and what is it good for? Thank you...
  2. Arty-Z7-20 board

    Hello @JColvin, here is my petalinux result: I think, that i must use the base Project "This petalinux project targets the Vivado block diagram project found here: https://github.com/Digilent/Arty-Z7-20-base-linux.". If i do so, then i get the following Problem: There are four ip-cores used that are not available in the current vivado Suite. i can not use the example because of the unknown ip-cores. Can you give me the smallest and easiest vivado-system that is able to host a Linux OS? Thank you...
  3. Arty-Z7-20 board

    Hello @JColvin, for your info: The filenames are too long in the base-linux Project which is needed for the petalinux Project. but if i reconfigure my developement Environment and use a Directory called "work" in the root Directory than it works (Windows 7 64-bit). Best regards deppenkaiser
  4. Where is J14?

    Hello @BodganVanca, very nice! Thank you... Now i have contact with three Forum-member, i hope you are not worry about that? I will now take a look at the Linux System. Thank you...
  5. Unknown Resource

    @artvvb Thank you, now it works. I have an other question. I used the "Hello World" example in the SDK and it was good; how can i write code for both cores of the A9 (bare metal)? Thank you...
  6. Arty-Z7-20 board

    Hello @JColvin, thank you for your answer. I should tell you, that i'am now able to create a bare metal simple "Hello World" Project, but i must do more than expected (disable a lot of unused Hardware); but it's ok! I read the "bare metal" tutorial you gave me and i'am a bit confused because of this: "4.8 Click the Add IP button () and search for 'MicroBlaze'. Select MicroBlaze from the list of results and press Enter on the keyboard to continue." Why is there a microblaze? Today i will read and try the Linux example, i hope it creates less confusion :-) Everything is fine! Thank you...
  7. Where is J14?

    Already connected to port: COM9 Connected to COM10 at 115200 Hello World Ok, i did it... I must disable all other peripherals... Thank you!
  8. Where is J14?

    system.pdf Hello Vanca Bogdan, yes you are right, my language is bad and i apologise for that. But if i do what you told me, i can not reach my Goal. I deleted my small design and placed a Zynq ip-core - only that; then i run "block Automation" and after that "Generate Bitstream". So i get three Errors: [BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK [BD 41-1031] Hdl Generation failed for the IP Integrator design C:/Projekte/Masterthesis/Vivado/PU/PU.srcs/sources_1/bd/system/system.bd [Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution. To solve These errors i add the System Clock from the Arty Z7-20 ip-core section as you can see in the attached System.pdf. I earned that: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 132 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: reset_rtl. and [DRC UCIO-1] Unconstrained Logical Port: 1 out of 132 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: reset_rtl. So what do i wrong? Do i have the wrong inner attitude? I will write my Thesis and i Need a Linux based SoC because i have a fantastic idea - but it seems - i have no luck... Thank you...
  9. Unknown Resource

    Hello Bogdan Vanca, i have allready installed these files. If i create a new project, then i can choose the Arty-Z7-20 board as plattform. My Problem ist: I like to use the UART and in the board's ip-tab are some ip's for my board, but no ip for the UART. If i take the ip "uartlite" from Xilinx then i have not the right configuration and the Operation "Generate Bitstream" fails. So once again: "[..] takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length [..]". How do i connect or use or configure a design, that i can use the UART? Thank you.
  10. Where is J14?

    Hello, i'am still trying send "Hello World" to my terminal. I made a simple design in vivado and use the uartlite ip. But i cant generate the Bitstream because of undefined ports: "[DRC NSTD-1] Unspecified I/O Standard: 2 out of 132 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: uart_rtl_rxd, and uart_rtl_txd." So i tried to solve that issue, but i dont know which pins i should connect with the used ports. I thought, that i should read the manual, but the manuel gives me no answer! The page where J14 (USB-UART-Bridge) should be decribed is lost - maybe in the deep space or in an black hole? Where is the schematic for the Arty-Z7-20 board? I dont mean the one, where J14 is gone away. My trust in you is nearly gone... Thank you...
  11. Unknown Resource

    Hello, the online Manual wrotes: "[...] The Zynq presets file (available in the Arty Z7 Resource Center) takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length. [..]" Where are the files? What Name do they have? How do i use them? Thank you...
  12. Arty-Z7-20 board

    Hello, i have since a few days a new arty-z-20 board and i like to learn from the rare examples for that board. I found one example which seems to be the base for Linux (Arty-Z7-20-linux_bd-master). This example was made with the Vivado 2016.4 Suite, but i use the current Vivado Suite (2017.3). In that example are two ip`s that could not be upgraded, because they no longer exists in the current Vivado Suite. Where can i get some working examples with Vivado 2017.3 and higher Support for my new Arty-Z7-20 board? My first Arty board was the Artix-7 "original" board. I had found all the examples that i needed to learn from the beginning to the full scale microblaze architecture. I made good experiences, but now i'am not happy with that arty-Z7-20 board! How do i build the simplest Zynq architecture with UART and "bare metal" OS? How do i build the very easiest Linux architecture and what ip's do i need for that? I have a lot more questions... Thank you...