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  1. It doesn't matter, you reply makes me feel comfortable, a good day!
  2. Hi t all, actually I new to programming, some places may be completely unknown, but a period of time, I need to do some procedures to detect, but appear in the process of the problem is not so easily solved for me, so I want to seek some help. I have designed a system using Artix-7 FPGA on a custom board. The goal is to transfer 32 bit data to an external on-board chip whose data bus is an inout port. First, a little background: The external chip is driven by a 100MHz clock which is generated by the FPGA, let's call it o_clk. The FPGA generates this clock through an MMCM in the Memory Interface Generator (MIG IP) using the 200MHz differential system clock. The o_clk is looped back from the FPGA's output and is given to another ball as an input clock, let's call it i_clk. The external chip receives the o_clk and sees data on this clock's rising edge. However, when the external chip sends data back to FPGA, the FPGA sees this data on the looped back i_clk. The idea behind doing so is that we can treat communications as source synchronous, in both the directions (remember, it is an inout port). Something like below: FPGA --> EC is synchronous to FPGA because FPGA generates clock EC --> FPGA is synchronous to EC because FPGA gets external clock (virtually from EC) To constrain this design, I have used the i_clk to set input delays on the io_data and have used the o_clk to constrain output on the same io_data bus. I have made sure I am using a forwarded clock (create_generated_clock)(using the ODDR2) for the set_output_delay constraint. Here are my constraints: create_clock -period 10.000 -name i_clk -waveform {0.000 5.000} [get_ports i_clk] set_clock_groups -name loopback_grp -asynchronous -group [get_clocks i_clk] -group [get_clocks o_clk] set_input_delay -clock i_fx3_pclk -max 8.000 [get_ports io_fx3_fdata] set_input_delay -clock i_clk -min 2.000 [get_ports io_data] set_output_delay -clock o_clk -max 2.000 [get_ports io_data] set_output_delay -clock o_clk -min -0.500 [get_ports io_data] The system seems to work properly when I run it on hardware, but I still have some doubts because I am still an amateur FPGA developer and this is my first big FPGA design. My questions are: Have I designed a good system? Is it correct to treat the communication from EC --> FPGA as source synchronous? (The other direction is source sync because FPGA is providing clock, if I am not wrong.!) Are my constrains correct? Many thanks!