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About mishu

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    Analog & Digital Electronics, FPGA Based DaQ systems, Power supplies, Motor control applications

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  1. mishu

    DDR3 input clock source

    Hi, I am wondering why is a 100 MHz clock present on the ARTY-S7 to be used for the DDR3 clocking, but not present in the ARTY-7. Why not use only a single 100 MHz clock source for ARTY-S7 as main clocking source? Or this was the idea from the beginning? I suppose in both cases with a SE 100 MHz clock source placed on a MRCC FPGA pin can be used to clock also the FPGA resources and the external DDR3 device. Cheers, Mishu
  2. mishu

    FPGA ESD protection

    Hi, I notice that the newest digilent boards (e.g ARTY-S7 and ARTY-A7) dont have the TVS diodes on the GPIO connectors, but the oldest boards (e.g. NEXYS 4 DDR) have the TVS diodes on the GPIO connectors. I suppose that Digilent decided to use the FPGA I/O internal body diodes, hence the external ones are not needed, or is just a cost issue? Thanks, Mishu
  3. Hi there, As many users, I have a problem with my JTAG SMT3 device, it seems to stop working and to be seen in Vivado, for unknown reasons at this time. I would like to make it work again, so please maybe somebody can send me a PM message with the steps needed to be done to achieve this. Thanks, M.
  4. Hi @jpeyron , Right now is just a part of my PhD thesis. Indeed the flow control configuration seems robust to be used. Thanks, V.M.
  5. Hi @jpeyron, Sorry, but I dont understand what do you mean by external project. Regarding the second question, yes, the uart process both FPGA I am planning to be modular and user configurable depending on each application. Thanks, V.M.
  6. Hi, I have designed an UART core without any flow control for use with FPGA devices when communicating with LabVIEW. I am looking for a way to receive (from FPGA to LabVIEW) data fast and correctly, hence I am investigating the following configurations for setting the VISA READ when to start or stop reading UART bytes: 1-with termination char: this is very tricky in the binary world as are the FPGAs, because it can trigger false stops sooner than expected. A solution will be to use a custom 3 termination chars like "/n/n/n" and LabVIEW will read till will receive this sequence.
  7. mishu

    SPI Length

    Hi, Try to reconstruct the signals using trigger schmtt circuits, it should work. Also try to lower the SPI CLK if you dont need high sampling rates. M
  8. mishu

    JTAG-SMT3 3D step file

    Hi @Bianca, Awesome, many thanks. Cheers, M
  9. mishu

    JTAG-SMT3 3D step file

    Hi, It is possible to have the 3D step file for the Digilent JTAG-SMT3 device? I want to give a nice 3D view of my board. Thanks in advance! Cheers, M
  10. mishu

    FT2232HQ Digilent firmware

    Hi, Sorry for late reply. I manage to find a solution, hence I will just buy the JTAG-SMT3 module which is FT2232HQ based and will do what I need it for. Best, Vlad
  11. Hi, I am planning to design a custom FPGA board based on Artix-7 FPGA. The JTAG interface I plan to do it with FT2232HQ as ARTY-7 board. It it possible to get the firmware or project sources for the FT2232HQ to configure its EEPROM to work with JTAG and UART? Thanks in advance! Vlad
  12. Hi @JColvin, Awesome, seems like Altium accepted it. Looks amazing. Thanks a lot. Best Regards, Mishu
  13. Hi @Bianca, I was referring to A7. Thanks a lot for your data. It should be enough for me to do my work. Also I will be glad to have also the step file of the board. Just to have it connected with my board in my 3D layout. Best Regards, Mishu
  14. Hi, I there a way to get precisely some layout dimensions and coordinates for the Arty-7 Board? I am interested to have the PMOD's location with respect with an origin reference on the board. I know that it can be done with an ruler, but I had to ask. Thanks, Mishu
  15. @ [email protected] Thanks a lot Dan, for your info. I will study them, I shall be back once I am more familiar with. Thank you, Vlad