I had a look at the diligent repository on github and the zybo linux_bd project. It provides an HDF but no vivado block layout so I can't see the connections that need to be made.
Could you please expand on which connections are needed?. I have been trying to find what the magic is, and I'm sure there's a set of connections that need to be made. Other xilinx forum posts advocate editing the device tree and adding, or expanding the PHY section and add a MAC address, but you are saying here that a set of connections should be made so that u-boot and kernel generated code initialise the PHY and GEM correctly using I2C. On the new Zybo Z7, another post says the generated I/O pin set up doesn't match the circuit diagram and hence needs a different connection to be set up.
Having reviewed the circuit for the Zybo 7000 that digilent makes available (see RTL8211 from Zybo 7000) I can see pins MDIO and MDC are labelled ETI_MDIO and ETI_MDC. These are connected via the Zynq-7000 block configuration into P5_MIO53_501 and P5_MIO52_501 respectively. Further, the 24AA02E48 chip that stores a MAC address looks to be configured to use AC_SDA/AC_SCL - an i2C interface - to extract it's address. These pins are connected to IO_L13P_T2_MRCC_34 and IO_L23P_T3_34.
how do I check these are configured? If i look at my block design in vivado for Zynq - I see ENET_0 is on, but I don't know if it's got the MDIO/MDC connected, nor the SDA/SCL.
are these the only two items to connect to have it generate the right linux device tree?
Any other guidance you can give? I want to do a cycle where I design the Vivado project, it results in an HDF that petalinux can use to generate a good enough linux that it operates the ethernet ok. Just don't know where I'm going wrong.