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  1. db12321

    ARTY XDC Drive strength

    I am using an ARTY board. I have just used the constraints as is without making any changes. I do not see any constraints for drive strength or Slew rate attribute anywhere in the XDC file. I am wondering how it is determined that the default values are sufficient for these attributes. For example for the Ethernet PHY i browsed thru the datasheet but didnt see anything that would make it clear to select 12mA (default) drive strength for those pins.
  2. I read the pdf but it didnt address that. I havent reached out to them yet
  3. I followed the ARTY Microblaze server tutorial and was able to get it working. However I noticed that it does not use any input or output delay constraints. I was trying to understand how it is being designed so that these constraints are not needed as well as how to add the constraints so I can check the timing of those timing paths On receive side: If I am reading the PHY datasheet correctly the RXD data line transitions are centered at the falling edge of the 25 MHz RX_CLK with but possibly varying from 10ns to 30ns after the rising edge of the clock. a quarter period of the clock.So if I understand this correctly the constraints would be for each pin something like: set_input_delay -max 30 -clock [get_clocks rx_clock] [get_ports RXD[1]] set_input_delay -min 10 -clock [get_clocks rx_clock] [get_ports RXD[0]] Is this the correct way to constrain these? The Ethernetlite MAC in the reference design appears to handle the design by: 1. Delay the RXD data inputs with a ZHOLD_DELAY block. 2. Put the RX_CLK is put onto a global clock buffer 3. latch the output of the ZHOLD_DELAY with the global clock into IOB FFs on the rising edge of the clk. Is these a reason that this would be guaranteed to work without the clock constraint? Any comments would be much appreciated Thanks!
  4. I was interested in finding a board to learn about using gigabit transceivers as well as PCIe. Any suggestions on boards that arent too expensive? Thanks
  5. I am not really sure if this is the correct forum or not for this question. I purchased a Zybo board and am trying the Vivado tutorials linked udner the digilent classroom site. Specifically, I am trying to do the Embedded System Design Flow on Zynq using Vivado lab2 error using the Zybo board and Vivado 2014.2 webpack. When synthesizing the design it says synthesis completed sucessfully but with 16 errors. All of them are a variation of: [Runs 36-287] File does not exist or is not accessible:'c:/Users/David/Desktop/Tutorial_Projects/Xilinx_University_Projects/Embedded_System/lab2/lab2_try1/lab2_try1.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/738df366/hdl/processing_system7_bfm_v2_0_local_params.v' I looked for the folder and there is no /processing_system7_bfm_v2_0/ folder under xilinx.com in the directory. There is a folder for the processing_system7_v5_4 . I am not sure why the processing_system7_bfm_v2_0 folder wouldnt have been created. I would greatly appreciate any guidance or help. Thanks, Dave
  6. I am new to Vivado. I saw one of the files for the Zybo board is a board defintion XML file that it says is for configuring the Zynq in IP Integrator. However, I havent been able to figure out how to impor this information into Vivado. If someone could point me in the right direction or to the appropriate User Guide I would greatly appreciate it Thanks, Dave