Vishnuk

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  1. hi, below i have attached the block diagram image for uart ip core. can somebody tell me if it is right. i would appreciate if somebody could give me a step by step guide for the same.
  2. hi, i went through the pdf files on ipcore as suggested but, they haven t mentioned as to how to configure in vhdl. i was able to design the block diagram, generate hdl wrapper, but cannot modify it for my use. i want to know as to how do i modify the ipc ore for my use, after creating hdl wrapper.
  3. Hi, can somebody tell me how to use uart ipcore uisng vivado, basys 3 board. i want to configure the uart core for echo purpose can someone tell me how to do it. what are the steps ?
  4. Vishnuk

    creating a latch data

    the dfin value gets refreshed soon.for both the cases the value gets stored in buf for short instance and then vanishes
  5. Vishnuk

    creating a latch data

    Hi, i am receiving a data and then storing it in variable, i need it to hold that value untill new data arrives, the variable happens to hold data for few clock cycles and then vanish. Can somebody help me with it i tried below statements buf <= dfin when (valid = '1') else buf; process(clk) begin if (rising_edge(CLK)) then if valid ='1' then buf <= dfin; end if; end if; end process;
  6. hi actually i am new to this fpga, i dont understan how to instantiate. Can u tell me if i want to do uart echo how do i do it in vhdl ip core
  7. Hi, can anybody suggest me how to work on ipcore for basys 3 board , i need to integrate uart and fifo ipcore. can somebody tell me how to get started
  8. hi, Can somebody tell me how to use uart and fifo ipcore together using vivado for basys 3 board. i want to receive data thru uart and then write into memory. once memory full it should read out the memory through uart
  9. Hi, i wrote a vhdl code for fifo as given below, the depth of memory is 10 for 8 bit data width, however my memory full flag goes high when filled with 3 data it can be seen in the simulation image, the memory gets empty on reading out three elements. Can somebody please help me in fixing it. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity fifo is generic ( constant depth : positive := 10 ); --depth of fifo port ( clk : in std_logic; reset : in std_logic; enr : in std_logic; --enable read,should be '0' when not in use. enw : in std_logic; --enable write,should be '0' when not in use. data_in : in std_logic_vector (7 downto 0); --input data data_out : out std_logic_vector(7 downto 0); --output data fifo_empty : out std_logic; --set as '1' when the queue is empty fifo_full : out std_logic --set as '1' when the queue is full ); end fifo; architecture Behavioral of fifo is type memory_type is array (0 to depth-1) of std_logic_vector(7 downto 0); signal memory : memory_type :=(others => (others => '0')); --memory for queue. signal readptr,writeptr : integer := 0; --read and write pointers. signal empty,full : std_logic := '0'; begin fifo_empty <= empty; fifo_full <= full; process(Clk,reset) --this is the number of elements stored in fifo at a time. --this variable is used to decide whether the fifo is empty or full. variable num_elem : integer := 0; begin if(reset = '1') then data_out <= (others => '0'); empty <= '0'; full <= '0'; readptr <= 0; writeptr <= 0; num_elem := 0; elsif(rising_edge(Clk)) then if(enr = '1' and empty = '0') then --read data_out <= memory(readptr); readptr <= readptr + 1; num_elem := num_elem-1; end if; if(enw ='1' and full = '0') then --write memory(writeptr) <= data_in; writeptr <= writeptr + 1; num_elem := num_elem+1; end if; --rolling over of the indices. if(readptr = depth-1) then --resetting read pointer. readptr <= 0; end if; if(writeptr = depth-1) then --resetting write pointer. writeptr <= 0; end if; --setting empty and full flags. if(num_elem = 0) then empty <= '1'; else empty <= '0'; end if; if(num_elem = depth) then full <= '1'; else full <= '0'; end if; end if; end process; end Behavioral;
  10. Vishnuk

    uart fifo integration

    hi, i am trying to integrate fifo with uart, i basically want to know what is the relation between the read write cycle and the baud rate of uart. i actually want to know what determines the read write cycle of fifo.
  11. hi i am receiving data through uart of 8 bit data and want to store it in 16 bit memory . i will also be receiving 16bit data of adc through spi which is a 8 bit format, how do i append it in memory. can somebody help me with it
  12. Hi, I am new to FPGA, can somebody tell me how to use uart ipcore , how can we modify the vhdl code for the same. iam working on basys 3 board.
  13. Hi, Can somebody help me by sending a working UART vhdl code for echo test. i want to test it on my basys 3 board. Kind regards
  14. Vishnuk

    Fpga XADc

    Hi, i want to used fpga basys 3 xadc . i want to know what kind of interface to be used like when AXi -lite/stream and DRP interface is used and for what purpose? for example if i am connecting externally a voltage divider circuit with a potentiometer to the Xadc port , how do i do real time data monitoring?
  15. problem solved i used Vaux 15 instead of Vp VN channel. Thanks lot for the reply. I have a query though. i will be using xadc for reading a ccd image so inorder to read 1000 pixel whose analog signal will be around 1Mhz, what do i do jus use a for loop i.e for i=1 to 1000 data=getadc(channel); end is this the right method?