CKV

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Posts posted by CKV

  1. Hello @jpeyron

    I have upgraded the PMOD IP's for Virtex ultra scale+ (VCU118), How can I integrate this into my HDL design? (like for Xilinx IP's we have HDL stub, and I can instantiate stub in  my top HDL design ). 

    It seems to me, I need to use an AXI protocol between my top design and PMOD IP. Do you have any examples design? (Like for SDK we have this https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start) . 

     

    Thanks in Advance

     

  2. Thank you for your reply.

    I am providing 100MHz (10ns) clk to  VHDL module. when I am applying 3.3V between A1 and GND on spartan 6 it is showing FFFF and 0V between A0 and GND  it is showing 0000.

    Similarly ( clock is 100MHz), I have done on VCU118 but the results are not correct.(shown in image )

    Do you think is there any issue with the level shifter? I am using pmod in the default mode, I haven't done any level shifting.

       ILA_AD1.thumb.JPG.8fb29bde04723976db4c209c3b22ad1e.JPG

  3. Hello Jpeyron,

    I am using pmod in the default mode, I haven't done any level shifting, is that a problem? if so how to do the level shifting?pomd_pin.thumb.JPG.6315cdacbf9ca53a6f4d34965ba7a019.JPG e any level shifting, is

  4. Thank you, I have cross-checked the desigILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGn, I am attaching the image ILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGof observed signals on ILA, may help you identify the  probleILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGmILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPG   

    I have applied 1) 0V on D0 and 2) 3.3V on D1

    image.png

  5. Hello,

     

    The issue is I am trying use Pmod AD1 (ADC) for connecting to VCU118 pmod port, It is not giving an accurate conversion of analog input, the signal keeps changing (please see in the attached image) even when the analog input is constant?

    What would be the exact reason for this? 

    The same design I was implemented on the Nexys Spartan 6 board, it is working perfectly. Just I changed the XDC file for connecting to VCU118 (pins from AV16 to AT16)  

    Many thanks.

    adc.JPG

  6. Hello,

     

    can I get the HDL files for the PMOD AD1? Exactly I need code which can take the AD1 outputs D0 or D1 to HDL module and gives me the output has 12bit number. so that I can process these 12bit numbers in subsequent modules.

  7. Hi JColvin,

    Thank you for the reply. I can change from nexys 3 UCF to Virtex ultra scale+ XDC for those VHDL codes. The main module needs 100MHz clock, I can provide that frequency from one of the clock generators on Virtex ultra scale+.  What would be the maximum AD2 conversion rate?

  8. Hi JColvin,

    Can I use AD2 and DA1 simultaneously by connecting to my 12 pin pmod on virtex ultra scale+? I found reference VHDL codes in digilent for both so I am planning to use the AD2 and DA1, instead of AD1 and DA4. 

     

  9. Hi JColvin,

    Thank you for the reply. So now by using the pmod splitter cable, I can connect both ADC and DAC, also I can send and receive data from DA/AD simultaneously.  If I buy AD1 and DA4 from Digilent, will they provide example RTL code?  

  10. Hi JColvin,

    Thank you for the reply. I would like to use Pmod AD1: Two 12-bit A/D Inputs and Pmod DA4: Eight 12-bit D/A Outputs, Both are the 6-pin Devices. 

    My Board Virtex ultra scale+ have the 12 pin PMOD (8-I/O and 2-Vdd and 2-GND). Can I use 6pins for connecting  ADC and another 6pins for DAC Simultaneously?                                                       Here I am attaching my Board PMOD pin Information.

                image.thumb.png.0a1eedb14fb507330f60a4bdd5bfe4d0.png