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  1. One thing I realized in the course of mulling this question: Part of my early resistance to splitting pio[...] into pioA, pioB and pioC was that I wanted to implement a bus that would span those ranges, and had a mental block about how to achieve that. It's not very difficult, but in case someone else has the same hiccup, I'll post an example solution here: module top( input sysclck, output [1:0] led, input [14:1] pioA, input [23:17] pioB, input [48:26] pioC ); wire [8:1] mybus; assign mybus[4:1] = pioA[14:11]; assign mybus
  2. Hi @xc6lx45, Yeah, I ended up renaming and renumbering as well. I just figured if the xdc was supplied written as a discontinuous array, there must be some way to use it as such. Graham
  3. On Cmod A7, the xdc file lists pio[1] to pio[48], but there are gaps at 15,16 (which are instead analog input pins) and 24,25 (which don't exist). So when I create a Verilog top module that uses pio, how to I specify these discontinuous ranges? Conceptually I want: module top ( input sysclk, output [1:14, 17:23, 26:48] ) but obviously that's not valid syntax. So how DO you use the full set of pio's as written in the xdc file? The file in question:
  4. Thanks @xc6lx45, for providing a very thoughtful answer.
  5. I chose 6 cpus, but it only appears to use 1 to 2 as I mentioned, and 8G RAM in the system. The board is the Cmod A7 Artix 7-35. The project is about as minimal as you can get and still have it do something observable. Well I supposed it could be reduced to a 1-bit counter with 1 output. But I wanted it to be visible on LEDs. :-).
  6. Hi folks. Could someone give me a reality check on how fast the Vivado tool chain is expected to run? I mean the entire Synthesis, Implementation, Generate Bitstream sequence. Here's what I get on a simple "hello world" design involving a single top.v with a simple 40-bit counter, sending 8 outputs to pins, no additional IP, targeting a CMod A7-35. I am using pretty much out-of-the-box settings in Vivado, so far as I am aware. If I make a minor change to top.v, then click on "Generate Bitstream", this invokes the entire chain (no surprise), which takes a total of over 3 minutes
  7. ... and not being able to stand the suspense, I just tried out my conclusions from that last post, and indeed the following settings work with no smoke. CONFIG_VOLTAGE: 3.3 CFGBVS (Configuration Bank Voltage Selection): VCC0 (selects high range of I/O voltages) For what it's worth, these settings end up in the xdc file: set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] ... and I'm not sure why they aren't part of the default xdc that Digilent supplies. It would be interesting to know if any other values are valid, given the Cmod A
  8. Hi @[email protected], thanks again for your comments. I now have a sample which avoids warning messages (mostly, see below). I show it below for others who may stumble in here with the same questions. The key element for avoiding the RPBF-3 DRC warnings (as [email protected]) said) is to treat the I/Os either as unidirectional inputs or outputs (and let Vivado sort out the appropriate configuration) or to treat them explicitly as a tristate output driver plus an input buffer, using the IOBUF primitive. Below are an xdc file and module that use the former strategy. ## xdc file for demo_counter # Clock sig
  9. @[email protected] Thanks for the advice, yes I realize that the inout IOs really consist of an output, its tristate control, and its input. What I don't understand is how to explicitly or implicitly tell Vivado/Verilog how to configure that. I have modified @JColvin 's example with what I think you're suggesting (see below), but I'm still getting RPBF-3 DRC warnings on all of pio[9..1] (the 8-bit counter.output, and the 1 bit enable input.) Any further ideas? Thanks. module top (clk, pio); input clk; inout [9:1] pio; reg [31:0] counter_0 = 0; // count clock cycles reg [ 7:0]
  10. Hi folks, I'm using some very basic examples with Cmod A7, which work in the sense that they result in a behaving FPGA. However, I'm trying to get rid of, or at, least understand the various warnings. One warning that occurs for all examples I tried is: CFGBVS-1#1 Warning Missing CFGBVS and CONFIG_VOLTAGE Design Properties Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage
  11. Hi JColvin -- thanks for that project, it was helpful getting started. Especially after I realized that pin 1 is at the Pmod end, not the USB end :-). Couple of followups -- I think there might be an issue in the xdc file: set_property ... [get_ports clk] create_clock ... [get_ports sysclk] ... I think the two clock names should match. At least, Vivado gave me a warning until I changed the second one to 'clk'. Now, a question: I get warnings for all the I/Os as follows: [DRC RPBF-3] IO port buffering is incomplete: Device port pio[1] expects both input and output buffer
  12. Thanks jcolvin and Dan, I will look into those projects. -- Graham
  13. Thanks for your response, but ... that's pretty disappointing. Having, before purchase, taken note of the fact that demos were available, I thought they would actually contain code showing known good examples, so we would be off-to-the-races with hardware we could exercise, and revise to use other I/Os. As a non-student customer, withholding that code subtracts value from the product -- it's just a time-wasting obstacle. As for the xadc project, it only exercises inputs, and at that analog inputs. These are not of interest at the moment. In fact it was only belatedly that I discovered tha
  14. I'm wondering where do we find the source for the Cmod A7 Stopwatch demo? One the demo's page ( I can only find links for the bit and bin files. Since this is the only one of the Cmod A7 demos that exercises the pins (as opposed to on-board features), it would be useful to have a known-good demo project to modify. Thanks!
  15. OK thanks. Yes, updating that tutorial would save a lot of time and confusion. I later noticed that Xilinx's page for 2017.2 has a bit more description relating to free WebPACK than the page for 2017.3, though it's still not clear how to invoke the free aspect. Further confusion is added by the Xilinx page you arrive at from Vivado's License Manager, as that page omits the Activation-based licenses, and the licenses it does show include a Free one for pre-2015, as though you can't license 2016 and later for free. Evidently that doesn't mean you can't use 2016 and later, it means that no l