rockxito32

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  1. rockxito32

    PmodACL I2C Zedboard -- Getting Started with Digilent Pmod IPs

    Hi @jpeyron Thank you for your time. After a long time and fail tests, I done successfully the test of SPI communication between PmodACL and Zedboard, just as it is in the tutorial "Getting Started with Digilent Pmod IPs", these are some pictures: By other hand, I tried to build the I2C communication between PmodACL and Zedboard but when debugging the SDK code, it's keeps in a while of a register that I don't know how change it: This is my full project created in Vivado 2015.4: https://we.tl/v8XpXoyKvH
  2. rockxito32

    Usign multiple PmodACL with Zedboard by SPI

    Thank you for your soon response Then, it'll be something like that: #include "xparameters.h" #include "xil_cache.h" #include "PmodACL.h" #include <stdio.h> #ifdef __MICROBLAZE__ #include "microblaze_sleep.h" #else #include <sleep.h> #endif void DemoInitialize(); void DemoRun(); void DemoCleanup(); void DemoSleep(u32 millis); void EnableCaches(); void DisableCaches(); PmodACL acl; PmodACL acl1; int main(void) { DemoInitialize(); DemoRun(); DemoCleanup(); return 0; } void DemoInitialize() { EnableCaches(); ACL_begin(&acl, XPAR_PMODACL_0_AXI_LITE_GPIO_BASEADDR,XPAR_PMODACL_0_AXI_LITE_SPI_BASEADDR); ACL_begin(&acl1, XPAR_PMODACL_1_AXI_LITE_GPIO_BASEADDR,XPAR_PMODACL_1_AXI_LITE_SPI_BASEADDR); ACL_SetMeasure(&acl, 0); ACL_SetMeasure(&acl1, 0); ACL_SetGRange(&acl, ACL_PAR_GRANGE_PM4G); ACL_SetGRange(&acl1, ACL_PAR_GRANGE_PM4G); ACL_SetMeasure(&acl, 1); ACL_SetMeasure(&acl1, 1); ACL_CalibrateOneAxisGravitational(&acl, ACL_PAR_AXIS_ZP); ACL_CalibrateOneAxisGravitational(&acl1, ACL_PAR_AXIS_ZP); DemoSleep(1000); // After calibration, some delay is required for the new settings to take effect. } void DemoRun() { float x, y, z; while (1) { ACL_ReadAccelG(&acl, &x, &y, &z); printf("PmodACL 0"); printf("X=%f\tY=%f\tZ=%f\n\r", x, y, z); DemoSleep(1000); ACL_ReadAccelG(&acl1, &x, &y, &z); printf("PmodACL 1"); printf("X=%f\tY=%f\tZ=%f\n\r", x, y, z); DemoSleep(1000); } } void DemoCleanup() { DisableCaches(); } void DemoSleep(u32 millis) { #ifdef __MICROBLAZE__ MB_Sleep(millis); #else usleep(1000 * millis); #endif } void EnableCaches() { #ifdef __MICROBLAZE__ #ifdef XPAR_MICROBLAZE_USE_ICACHE Xil_ICacheEnable(); #endif #ifdef XPAR_MICROBLAZE_USE_DCACHE Xil_DCacheEnable(); #endif #endif } void DisableCaches() { #ifdef __MICROBLAZE__ #ifdef XPAR_MICROBLAZE_USE_DCACHE Xil_DCacheDisable(); #endif #ifdef XPAR_MICROBLAZE_USE_ICACHE Xil_ICacheDisable(); #endif #endif }
  3. rockxito32

    Usign multiple PmodACL with Zedboard by SPI

    Hi everyone, In this opportunity I want to establish a SPI communication between two PmodACL and a Zedboard, in Vivado software I done it this way: And I got the Bitstream file without any mistake. But how can I do the SDK configuration for read two PmodACL at the same time?
  4. rockxito32

    PmodACL I2C Zedboard -- Getting Started with Digilent Pmod IPs

    Hi @jpeyron happy new year, Of Pmod ACL project I deleted the xdc, I'll do the test soon. By other hand, for use Pmod ACL by I2C, I done "Getting Started with Digilent Pmod IPs" tutorial for Pmod Temp3, but I have a lot of questions about how alter it for Pmod ACL: These are the pictures of my design Thanks for your help, I'll be waiting for answer. Best regards, Oscar
  5. rockxito32

    PmodACL I2C Zedboard -- Getting Started with Digilent Pmod IPs

    Hi @jpeyron Thank you in advance for your help. After correcting the mistakes and doubts I had, I was able to finish the tutorial "Getting Started with Digilent Pmod IPs". These are the changes made in my project: In a few days I will do the test with the Zedboard and I will send the results. The communication done in that tutorial, is only SPI communication? Now, I have a new question: How can I do I2C communication between PmodACL and Zedboard using pmod header J2? I could see that there is continuity between pins of the headers J1 and J2 as follow: If the connection is like that, I would think the configuration of the hardware in Vivado doesn't change, does it? But, I would think the software configuration in the SDK changes, such as the assignment of I2C address and the storage registers. So, is there an example or how can I create those lines of code for I2C? Regards, Oscar
  6. Hi everybody, thaks for your time. I'm a new Xilinx user and I'm learning about VHDL language and FPGA. In this opportunity, I want to establish a I2C communication between Zedboard and PmodACL. I'm implementing the tutorial "Getting Started with Digilent Pmod IPs", and I have some doubts: 1) I've installed the "vivado-library-2015.4-3", but when I search the info in board section about Pmod there is nothing: 2) When I click on "Generate Bitstream" I get this error: With this lines: Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 2 threads ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 8 out of 146 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 8 out of 146 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pmod_out_pin10_io, pmod_out_pin1_io, pmod_out_pin2_io, pmod_out_pin3_io, pmod_out_pin4_io, pmod_out_pin7_io, pmod_out_pin8_io, pmod_out_pin9_io. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin1_iobuf/IBUF (in pmod_out_pin1_iobuf macro) has no loads. An input buffer must drive an internal load. WARNING: [DRC 23-20] Rule violation (BUFC-1) Input Buffer Connections - Input buffer pmod_out_pin4_iobuf/IBUF (in pmod_out_pin4_iobuf macro) has no loads. An input buffer must drive an internal load. INFO: [Vivado 12-3199] DRC finished with 2 Errors, 2 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. I think it's because in the block design I could not open the Pmod corresponding to the Zedboard and then the pin assignment is not elaborated. So, how can i do to import the complete library for Zedboard pmod? Or, which is the order for Pmod pin assignment? Bests reggards, Oscar.