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  1. Thanks Dan, I read that post sometime last week. It did contain some ideas I hadn't considered before, especially the divide by pi example. And, after reading the various links you pointed me to, I think I'm getting a handle on what can go wrong with fabric-generated logic clocks.
  2. @Piasa Thank you for the response. Makes sense. @[email protected] Thanks again, interesting articles. I love your blog... I'm learning alot.
  3. Thanks for the reply Dan, I've heard the comments about edges on non-clocks but I've also seen plenty of example code where this is done on derived clocks. For example, the sample code for the Digilent PmodCLP (I reference here: ) includes a count-based microsecond clock rather than 1MHz clock generated from some IP core. The code then goes on to use the posedge for this clock to drive a fair bit of the state machine logic. Lots of example code seems to do this. Which makes me wonder if there are times it is okay, or that I should just not read too much into example code. And I've no
  4. I was reading Dan Gisselquest's blog (aka @[email protected]), in particular, this specific part of the one that goes into some detail about the ALU for his ZipCPU: always @(posedge i_clk) if (i_ce) begin c <= 1'b0; casez(i_op) 4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB 4'b0001: o_c <= i_a & i_b; // BTST/And 4'b0010:{c,o_c } <= i_a + i_b; // Add 4'b0011: o_c <= i_a | i_b; // Or 4'b0100: o_c <= i_a ^ i_b; // Xor 4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR 4'b0110:{c
  5. I just got a PmodCLP and downloaded the verilog files here: Specifically, the Nexys 3 Verilog Example - ISE 14.2 code. Since I'm using an Artix Arty board, I had to modify the pins used, and the reset is reversed (on the arty the ck_rst is 1 when pressed), but after that things worked fine. The Arty, like the Nexys 3 has a 100MHz clock. In looking at the code, however, I noticed two errors that make the code quite confusing: 1) In the first always block: // This process counts to