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Flux

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Posts posted by Flux

  1. On 7/5/2023 at 12:47 PM, zygot said:

    All nicely done, entertaining, and informative. If you are new to FPGA development these are worthwhile resources to investigate. I've been doing programmable logic design for over 40 years and I've enjoyed reading what's being offered. Nifty keen.

    Thank you. I plan to add video captures from the Nexys soon.

  2. Hello,

    I've added the Nexys Video to my nine-part FPGA Graphics tutorial series.

    https://projectf.io/posts/fpga-graphics/

    Quote

    In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. Along the way, you’ll experience a range of designs and techniques, from memory and finite state machines to crossing clock domains and translating C algorithms into Verilog.

    You can also follow the tutorials on Arty A7-35T, iCEBreaker, and Verilator/SDL simulation you can run on PC/Mac.

    All the designs are open source and available on GitHub: https://github.com/projf/projf-explore/

  3. On 4/30/2023 at 8:13 PM, zygot said:

    I hope that you didn't think that my thoughts were being critical. You are right that using tcl scripts to generate FPGA projects, and obtain configuration files, that work for any version of one vendors tools can be complicated and frustrating. That's why it's great that you started a thread on the subject. I don't know about you, but I'm hoping that it generates some constructive posts from a variety of people bothering to read it. Gems are usually easy to miss lying in the grass.

    I didn’t take your thoughts negatively. On the contrary, I value thoughtful feedback and insight. Stars, likes, up-votes, etc. are ten a penny, but thoughtful replies like yours are rare. As you say, I hope this thread garners further constructive responses.

     

  4. Thank you for your thoughtful comments, @zygot. I realise my post is scratching the surface of a complex and often frustrating topic. I hope it at least makes new users consider Tcl scripting.

    My viewpoint may differ from the vendor norm because I rarely use IP cores (except for memory controllers). For the hobbyist projects I work on, the arrival of RISC-V has made it practical to work almost entirely in Verilog. I use primitives, MMCME2, OSERDES2 etc., but via templates in Verilog.

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