Flux

Thank you. I plan to add video captures from the Nexys soon.

Hello, I've added the Nexys Video to my nine-part FPGA Graphics tutorial series. https://projectf.io/posts/fpga-graphics/ You can also follow the tutorials on Arty A7-35T, iCEBreaker, and Verilator/SDL simulation you can run on PC/Mac. All the designs are open source and available on GitHub: https://github.com/projf/projf-explore/

I didn’t take your thoughts negatively. On the contrary, I value thoughtful feedback and insight. Stars, likes, up-votes, etc. are ten a penny, but thoughtful replies like yours are rare. As you say, I hope this thread garners further constructive responses.

Thank you for your thoughtful comments, @zygot. I realise my post is scratching the surface of a complex and often frustrating topic. I hope it at least makes new users consider Tcl scripting. My viewpoint may differ from the vendor norm because I rarely use IP cores (except for memory controllers). For the hobbyist projects I work on, the arrival of RISC-V has made it practical to work almost entirely in Verilog. I use primitives, MMCME2, OSERDES2 etc., but via templates in Verilog.

Hello, I've posted a new tutorial on Project F covering Tcl build scripts with Vivado: https://projectf.io/posts/vivado-tcl-build-script/ It's surprisingly easy to automate building your design with Tcl. I wish I'd known this when starting out with my Arty board back in 2018. Anyway, I hope you find this useful, and please do let me know if you have any suggestions or spot any errors. Cheers, Flux