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  1. Hello, Yes I am trying to get the Vivado license...The board I am using is the Nexys3..I got a link explaining the changes to be made but though I am unable to get this done.
  2. Hello people, I am encountering a problem when i am trying to acquire a free license file...I am using Windows 8 and maybe the license i am trying is just not compatible with my windows...any suggestion where i can get the required license file??
  3. Hello Everyone, I actually wrote a code for serial to parallel conversion but when I am trying to test it, I am getting no results. I am using a light sensor as input and then it passes through an adc (in this case an arduino) and then the digital form of the input is fed to the FPGA which carries out the serial to parallel conversion. At first i tried to synchronise the FPGA and the arduino by using same frequency but I could not reproduce 490Hz (arduino) for the FPGA. I am confused as to where there might be an error. Codes for Serial to Parallel: # library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity serial is port( S1 : in STD_LOGIC; clk : in STD_LOGIC; x : in STD_LOGIC_VECTOR(0 downto 0); P1 : out STD_LOGIC_VECTOR(7 downto 0) ); end serial; architecture serial of serial is component Dff is port ( clk : in STD_LOGIC; Din : in STD_LOGIC; Q : out STD_LOGIC ); end component; signal s: std_logic_vector (7 downto 0); signal i: integer :=1; signal clk1 : std_logic; begin clk1 <= clk and x(0); A0: Dff port map ( clk => clk1, Din => S1, Q => s(0) ); M1 : for i in 1 to 7 generate Ai: Dff port map ( clk => clk1, Din => s(i-1), Q => s(i) ); P1 <= s; end generate M1; end serial; # codes for Dff: # library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity Dff is port( clk : in STD_LOGIC; Din : in STD_LOGIC; Q : out STD_LOGIC ); end Dff; architecture Dff of Dff is begin process (clk ,Din) begin if (rising_edge (clk)) then Q <= Din; end if ; end process; end Dff; # codes for debounce: # library IEEE; use IEEE.STD_LOGIC_1164.all; entity debounce is port( input : in STD_LOGIC; cclk : in STD_LOGIC; clr : in STD_LOGIC_VECTOR (0 downto 0); output : out STD_LOGIC ); end debounce; architecture debounce of debounce is signal d1, d2, d3: STD_LOGIC; begin process (cclk, clr(0)) begin if clr(0) = '1' then d1 <= '0'; d2 <= '0'; d3 <= '0'; elsif cclk'event and cclk = '1' then d1 <= input; d2 <= d1; d3 <= d2; end if; end process; output <= d1 and d2 and not d3; end debounce; codes for clkdiv : # library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity clkdiv is port( mclk : in STD_LOGIC; clr : in STD_LOGIC_VECTOR(0 downto 0); clk : out STD_LOGIC_VECTOR (2 downto 0); clk47: out STD_LOGIC; clk381:out STD_LOGIC ); end clkdiv; architecture clkdiv of clkdiv is signal q: STD_LOGIC_VECTOR (23 downto 0); begin process (mclk ,clr(0)) begin if clr(0)= '1' then q <= X"000000" ; elsif mclk 'event and mclk = '1' then q <= q + 1; end if ; end process; clk(0)<= q(0); clk(1)<= q(1); clk(2)<= q(18); clk381<= q(17); clk47<= q(20); end clkdiv; ## codes for top level ## library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity serial_top is port( JB1 : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(1 downto 0); clk : in STD_LOGIC; led : out STD_LOGIC_VECTOR(7 downto 0) ); end serial_top; architecture serial_top of serial_top is component clkdiv port( mclk : in STD_LOGIC; clr : in STD_LOGIC_VECTOR(0 downto 0); clk : out STD_LOGIC_VECTOR(2 downto 0); clk47 : out STD_LOGIC; clk381 : out STD_LOGIC); end component; for all: clkdiv use entity work.clkdiv(clkdiv); component serial port( S1 : in STD_LOGIC; clk : in STD_LOGIC; x : in STD_LOGIC_VECTOR(0 downto 0); P1 : out STD_LOGIC_VECTOR(7 downto 0)); end component; for all: serial use entity work.serial(serial); component debounce port( input : in STD_LOGIC; cclk : in STD_LOGIC; clr : in STD_LOGIC_VECTOR (0 downto 0); output : out STD_LOGIC); end component; for all: debounce use entity work.debounce(debounce); signal clk381: STD_LOGIC; signal output: STD_LOGIC; begin Label1 : serial port map( S1 => output, clk => clk381, x(0) => sw(1), P1 => led ); Label2 : clkdiv port map( mclk => clk, clr(0) => sw(0), clk381 => clk381); Label3 : debounce port map( input => JB1, cclk => clk381, clr(0) => sw(0), output => output ); end serial_top; ####
  4. Sir, Doing this surely reduces the code lines but how to get the other parallel outputs????
  5. Hello Mr JColvin, I rewrote the codes for serial to parallel conversion but problem is that I am able to convert only 1 8-bit parallel..the other 6 outputs are just similar.. My serial input in simulation is 20 bit so basically I should have at least 2 8-bit parallel output but thats not the case :/ please can you help ??? library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity SIPO is generic (N: integer := 7); port( clk : in STD_LOGIC; Din : in STD_LOGIC; Q :out STD_LOGIC_VECTOR(7 downto 0); P1 : out STD_LOGIC_VECTOR(7 downto 0); P2 : out STD_LOGIC_VECTOR(7 downto 0); P3 : out STD_LOGIC_VECTOR(7 downto 0); P4 : out STD_LOGIC_VECTOR(7 downto 0); P5 : out STD_LOGIC_VECTOR(7 downto 0); P6 : out STD_LOGIC_VECTOR(7 downto 0); P7 : out STD_LOGIC_VECTOR(7 downto 0) ); end SIPO; architecture SIPO of SIPO is component Dff is port ( clk : in STD_LOGIC; Din : in STD_LOGIC; Q : out STD_LOGIC ); end component; signal s: std_logic_vector (7 downto 0); signal i: integer := 1; constant num_cycles: integer := 56; begin M1 : for i in 1 to num_cycles generate u0: Dff port map ( clk => clk, Din => Din, Q => s(0) ); u1: Dff port map ( clk => clk, Din => s(0), Q => s(1) ); u2: Dff port map ( clk => clk, Din => s(1), Q => s(2) ); u3: Dff port map ( clk => clk, Din => s(2), Q => s(3) ); u4: Dff port map ( clk => clk, Din => s(3), Q => s(4) ); u5: Dff port map ( clk => clk, Din => s(4), Q => s(5) ); u6: Dff port map ( clk => clk, Din => s(5), Q => s(6) ); u7: Dff port map ( clk => clk, Din => s(6), Q => s(7) ); end generate M1; L1: for i in 1 to 8 generate P1 <= s; end generate L1; L2: for i in 9 to 16 generate P2 <= s; end generate L2; L3: for i in 17 to 24 generate P3 <= s; end generate L3; L4: for i in 25 to 32 generate P4 <= s; end generate L4; L5: for i in 33 to 40 generate P5 <= s; end generate L5; L6: for i in 41 to 48 generate P6 <= s; end generate L6; L7: for i in 49 to 56 generate P7 <= s; end generate L7; end SIPO;
  6. 1116345

    Nexys3 Board

    Thanks Mr JColvin
  7. 1116345

    Nexys3 Board

    Hello, Actually I power my board via the USB cable...but the port through which I connect the USB has been loosen --' and I can't neither power the board nor program it...I think there is a sort adapter which can be used but I am unable to power it using it...and I think one can use pendrive by putting only the .bit file in it and thus carry out programming....Can anyone help????
  8. Hi, I tried another code but I am getting errors again . Can you please help me out?? CODE: library IEEE; use IEEE.STD_LOGIC_1164.all; entity pwm is port( clr : in STD_LOGIC; clk : in STD_LOGIC; pwm : out STD_LOGIC ); end pwm; architecture pwm of pwm is signal count: STD_LOGIC_VECTOR (7 downto 0); signal duty: STD_LOGIC_VECTOR (7 downto 0); signal period: STD_LOGIC_VECTOR (7 downto 0); begin P1: process (clk,clr) begin count <= X"00"; duty <= X"64"; -------------------------------------------------------------------------ERROR period <= X"F3"; -------------------------------------------------------------------------ERROR if clr = '1' then count <= (others =>'0') ; elsif clk'event and clk = '1' then if count = period - 1 then count <= count + 1; end if; end if; end process P1; pwmout: process (count) begin if count < duty then pwm <= '1'; else pwm <='0'; end if; end process pwmout; end pwm; ERRORS: # Error: COMP96_0015: pwm.vhd : (24, 12): ';' expected. # Error: COMP96_0015: pwm.vhd : (25, 14): ';' expected.
  9. Hello I did try this and the number of errors just increased.... ERRORS: # Error: COMP96_0077: PWM.vhd : (38, 13): Undefined type of expression. Expected type 'STD_ULOGIC' # Error: COMP96_0071: PWM.vhd : (40, 23): Operator "-" is not defined for such operands. # Error: COMP96_0077: PWM.vhd : (40, 7): Undefined type of expression. Expected type 'BOOLEAN'. # Error: COMP96_0077: PWM.vhd : (41, 14): Undefined type of expression. Expected type 'STD_ULOGIC'. # Error: COMP96_0071: PWM.vhd : (43, 22): Operator "+" is not defined for such operands. # Error: COMP96_0077: PWM.vhd : (43, 14): Undefined type of expression. Expected type 'STD_ULOGIC'. # Error: COMP96_0264: PWM.vhd : (49, 19): Signal "duty" in the sensitivity list must denote a signal that can be read.
  10. Hello, can someone help me with this error?? Thanks in advance code: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity PWM is port( clr : in STD_LOGIC; clk : in STD_LOGIC; duty : out STD_LOGIC; period : out STD_LOGIC; pwm : out STD_LOGIC ); end PWM; architecture PWM of PWM is component clkdiv port( mclk : in STD_LOGIC; clr : in STD_LOGIC; clk1 : out STD_LOGIC; clk95 : out STD_LOGIC ); end component; signal count : STD_LOGIC; begin U1 : clkdiv port map( mclk => clk, clr => clr, clk1 => period, clk95 => duty); end; begin <-------------------------------------------------------ERROR IS HERE clk4 : process(clk, clr) begin if clr = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then if count = period -1 then count <= (others => '0'); else count <= count + 1; end if ; end if ; end process clk4; pwmout: process(count,duty) begin if count < duty then pwm <= '1'; else pwm <= '0'; end if ; end process pwmout; end PWM; code for clkdiv: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity clkdiv is port( mclk : in STD_LOGIC; clr : in STD_LOGIC; clk1 : out STD_LOGIC ; clk95 : out STD_LOGIC ); end clkdiv; architecture clkdiv of clkdiv is signal q: STD_LOGIC_VECTOR (23 downto 0); begin process (mclk,clr) begin if clr= '1' then q <= X"000000" ; elsif mclk'event and mclk = '1' then q <= q + 1; end if ; end process; clk1 <= q(5); clk95 <= q(19); end clkdiv; ERROR: # Error: COMP96_0016: PWM.vhd : (35, 4): Design unit declaration expected.
  11. 1116345

    Programming

    Hello again, I was thinking of using microstepping....but it seems much more complicated than half and full steps... for full steps: when "00" => dout <= "1000" when "01" => dout <= "0100" when "10" => dout <= "0010" when "11" => dout <= "0001" for half steps: when "000" => dout <= "1000" when "001" => dout <= "1100" when "010" => dout <= "0100" when "011" => dout <= "0110" when "100" => dout <= "0010" when "101" => dout <= "0011" when "110" => dout <= "0001" when "111" => dout <= "1001" for microsteps (16 steps): when "0000" => dout <= "1000" when "0001" => dout <= when "0010" => dout <= "1100" when "0011" => dout <= when "0100" => dout <= "0100" when "0101" => dout <= when "0110" => dout <= "0110" when "0111" => dout <= when "1000" => dout <= "0010" when "1001" => dout <= when "1010" => dout <= "0011" when "1011" => dout <= when "1100" => dout <= "0001" when "1101" => dout <= when "1110" => dout <= "1001" when "1111" => dout <= for full steps: when "00" => dout <= "1000" when "01" => dout <= "0100" when "10" => dout <= "0010" when "11" => dout <= "0001" its seems that this is not possible and am sorry to bother u people on such an occasion.....By the way Merry Christmas to all
  12. 1116345

    Programming

    Hello JColvin and Hamster, I was thinking about the clock and position of sun and some calculations but then there is no use of sensors...it becomes a chronological tracker... My problem is that my sensors being on a separate platform, its difficult to make the solar panel accurate...
  13. 1116345

    Programming

    Thanks Sir, For the motor, I thought I would use PWM to control its speed but I do not think its a good idea...and i dnt knw if microstepping can be done...I wanted to rotate the solar panel by 1 degree untill the particular sensor is at its maximum....Actually I am using 7 sensors which are not on the solar panel but are on a separate platform...This enables to handle more than 1 solar panel with least number of sensors..But this also increases the difficulty as I am unable to design how to make the 2 motors rotate if you can help, I would be grateful..
  14. 1116345

    Programming

    Thanks Mr JColvin and Mr Hamster I am stuck with these if-elsif...Actually using my basics of C programming, I tried to write these codes...I attached a flowchart above and what I did was converting the latter into codes...What I want to program is that I have 7 values from 7 light sensors...I am comparing the values such that the light sensor will maximum value among the others thus causing the motor to rotate till that particular sensor is at its maximum value. Sensor 5 and sensor 6 are for the seasonal change in angle.....I actually want to design a solar tracker.
  15. 1116345

    Programming

    Hello Everyone, I am encountering some errors with my codes.Being a beginner, I dn't know much about loops.. I tried to use multiple looping but i cn't reach a proper result....can anyone help??? and PFA my flowchart my codes are as follows: library IEEE; use IEEE.STD_LOGIC_1164.all; entity comparator is generic (N : integer := 6); port( S : in STD_LOGIC_VECTOR(N-1 downto 0); Z : out STD_LOGIC_VECTOR(2 downto 0) ); end comparator; architecture comparator of comparator is begin process(S) begin comp1: for N in 0 to 4 loop -- for the sensors 0-4-- if S(N) < S(N-1) then N <= N+1; elsif ( comp2: while ( S(N)= '1')loop ) then --for S(N) < max value -- Z(0) <= 1 ; --rotate in specific direction-- end loop comp2; elsif N = '4' then Z(1) <= 1; --reset motor that is return to initial position -- else N <= N+1; end if; end if; end if; end loop comp1; if S(5) > S(2) then Z(2) <= 1 ;-- second motor is rotated -- end if; end process; end comparator; end comparator; and here are the errors: # Compile... # Warning: DAGGEN_0523: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available. # File: c:My_Designscomparatorcomparatorsrccomparator.vhd # Compile Entity "comparator" # Compile Architecture "comparator" of Entity "comparator" # Error: COMP96_0015: comparator.vhd : (22, 16): ')' expected. # Error: COMP96_0019: comparator.vhd : (22, 18): Keyword 'then' expected. # Error: COMP96_0019: comparator.vhd : (22, 41): Keyword 'end' expected. # Error: COMP96_0111: comparator.vhd : (25, 13): Labels do not match. # Error: COMP96_0019: comparator.vhd : (27, 10): Keyword 'end' expected. # Error: COMP96_0019: comparator.vhd : (31, 10): Keyword 'end' expected. # Error: COMP96_0016: comparator.vhd : (32, 14): Design unit declaration expected