JColvin

Hi @ajeetsinha2003,
I have sent you a PM.
Thanks,
JColvin

Hi @PDonnelly,
I have not heard anything about that variant of the JTAG SMT2 being discontinued.
I'm not involved in that aspect of the business, but I believe the -B is indicating baked, or at least the MSL 3 option.
You should be able to learn more (including the important 'can I still order this' ) by contacting our Sales department here: https://digilent.com/shop/sales-and-order-support/.
Thanks,
JColvin

Hi @Eminem,
Direct downloads for the images can be found for the Genesys ZU 3EG and the Genesys ZU 5EV on our Github here and here (SDImager recommended for Windows, "dd" for Linux) respectively (for the Rev D versions of the board), with the source for those images being available here and here.
There are some more instructions on using the out of box demo itself available on our reference site here: https://digilent.com/reference/programmable-logic/genesys-zu/getting-started#using_the_out-of-box_image.
Thanks,
JColvin

uses the same 2.1 mm barrel diameter found on the Zybo. This one should work: https://digilent.com/shop/5v-2-5a-switching-power-supply/ 
 

https://fpgaer.tech/?p=533 - Part 1, what is an arbiter?
https://fpgaer.tech/?p=542 - Part 2, implementing and testing a fixed-priority arbiter
https://fpgaer.tech/?p=622 - Part 3, Round-robin VHDL arbiter, code and testbench

I often use a UART for debug and as a user interface for projects. 921600 baud that can be used with any serial terminal program is nice for some things but sometimes you need a faster, more flexible interface. Here I provide an FPGA interface that uses 4 pins and a separate FT4332H or similar mini-module to access design resources 1.2 MiB/s full duplex. The first demo is for the CMOD-A735T.
The demo has something of interest for most readers besides a faster UART.
CMODA35T_DBUG_DEMO_R1.zip

Hi @mahinay,
None of the Digilent staff have used the Kria boards, but I would be very surprised if Xilinx's Vitis software did not support Xilinx's Kria devices. UG1400 doesn't indicate that there is a premade platform for them, but UG973 indicates that Vivado does support all Kria boards so you would be able to set up your hardware in Vivado and then export your hardware specification for Vitis to use.
Thanks,
JColvin

Hi @fp99,
You don't need to do anything particularly different.
We have a demo for the Pmod VGA on the Zybo Z7 that uses two differential Pmod ports on the Zybo Z7 (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pmod-vga-demo/start) and looking at the .xdc for the project (https://github.com/Digilent/Zybo-Z7-20-Pmod-VGA/blob/master/src/constraints/Zybo-Z7-Master.xdc) there is not anything fancy done for those differential ports, just the normal naming of the pins to match the name of the signal used in the design.
Thanks,
JColvin

Hi @Udayan Mallik,
I am not certain which exact error you are getting as I cannot see the error code in the Message console in your screenshots.
If I had to guess as what error your receiving, my guess would be that Vivado is saying that it cannot properly connect the pins 7, 8, 9, and 10 of the Pmod AD1. You can fix this by deleting the "pmod_jb" port and then right-clicking on the Pmod Out interface and choosing the Make External option.
After the interface has been made external and you make the wrapper for the project, you can find the correct names to explicitly name the Pmod pins in the .xdc by finding their names in the wrapper.v file. There are a couple of screenshots showing what I am attempting to describe in this post here:
Please let me know if you have any questions about this process.
Thanks,
JColvin

Hi @robb,
I unfortunately did not get the opportunity to adjust the HDL and .xdc to the pins you wish to use, but the problem you are running into is that the silkscreen pin number of the analog input pins is not necessarily the same as the XADC channel number in the Zynq processor in the Arty Z7 itself.
Based on page 9 of the schematic on Bank 35, https://files.digilent.com/resources/programmable-logic/arty-z7/arty-z7-d0-sch.PDF, the chipkit A0 through A5 (correspondingly named CK_AN<X>_P) are associated with the following channel numbers on the channel sequencer (which you can tell based on the "_AD#P" portion of the actual pin name on the Zynq chip).
CK_AN0 = vauxp1
CK_AN1 = vauxp9
CK_AN2 = vauxp6
CK_AN3 = vauxp15
CK_AN4 = vauxp5
CK_AN5 = vauxp13
After enabling those channels, the .xdc would need to be adjusted to correctly enable those pins (a master .xdc listing all of the pins is available here https://github.com/Digilent/digilent-xdc/blob/master/Arty-Z7-10-Master.xdc)
As for why this isn't better detailed or explained in the reference manual or the demo page is a great question; I have put in a request to get this corrected, though with the Thanksgiving week here in the US I do not anticipating this happening until at least next week. I should be able to help you further with this project then as well.
Please let me know if you have any questions.
Thanks,
JColvin

Hi @SASuba360,
Yes, the Analog Discovery 2 uses ADCs for its analog inputs, although as noted in the Analog Discovery 2 specifications, https://digilent.com/reference/test-and-measurement/analog-discovery-2/specifications, the resolution is only 14 bits.
In WaveForms, there is a FFT view option within the Scope tool,

as well as a more expansive option available in the Spectrum tool:

There is also a AnalogIn_FFT.py example that comes with WaveForms SDK:

Let me know if you have any questions.
Thanks,
JColvin

Hi @Engineer_Dude,
The Revision F schematic should be available in its Resource Center under Documentation: https://digilent.com/reference/programmable-logic/zedboard/start#documentation.
Thanks,
JColvin

Your board revision is written on the silkscreen just below the barcode. Our published schematics are generally correct. Designators do not have to be sequential and some components can be left not loaded. Digilent does not publish board layouts.

Hi @Udayan Mallik,
The Pmod ACL2 IP would not be able to acquire data from the Pmod AD1; while they both use the SPI protocol, the two modules have different SPI clock frequencies, registers to manipulate, and different bit lengths of data.
I would instead recommend you use the existing Pmod AD1 IP for the Pmod AD1.
Let me know if you have any questions.
Thanks
JColvin

Your question is similar to one that I responded to a while ago: https://forum.digilent.com/topic/4784-s3-starter-board-programmer/

You may not have this board but might find the project, which includes sources, interesting. With luck, maybe eve useful.

Welcome to the Digilent Forum @dcnorris!

Hi @H_M,
There is not any particular recommended multiplexer that would do as you are describing.
Mechanical switches that let you route a single source to one of multiple options certainly exist, though I do not have a recommendation of one that would avoid adding any additional impedance to the system. Also since the Impedance Analyzer board uses a terminal block to latch onto whatever wires from the DUT, there will inevitably be some degree of (at least visually) jerry-rigging the setup.
Thanks,
JColvin

I found it: You can set it in the "Supplies" tab, it didn't work at first because I had the tab opened twice.

Hi @Balnazzar,
I spoke with somebody on the Digilent Sales team and they let me know that Distrelec might be another option for an academic discount (I don't personally know the details). If you have further questions on pricing and where you might be able to get the best pricing options, I would recommend contacting the Digilent sales team directly through the Sales and Support order form, https://digilent.com/shop/sales-and-order-support/, where you can get the most accurate information regarding pricing options directly and not have to go through a "middle-man".
Technical questions on how to use Digilent products is still best put here on the Digilent Forum as the Order and Sales team will just end up forwarding your question on to me anyways.
Thanks,
JColvin

Hi @John J,
I was able to get the UART1 PS selftest (and external loopback) working with EMIO. In my initial test I had forgotten to make the UART1 module on the UltraScale+ IP in the block design external (and then of course constrained them to a pair of external pins, in this case a pair of Pmod pins). With regards to the XUartPs_SelfTest, a return of zero is a successful test (i.e. no error codes thrown). I've provided the main.c that I used (which also has 4 buttons and LEDs enabled in the hardware design so that pushing one of the buttons lights up all of the LEDs; this can be commented out of course).
The UART1 channel does not have its own COM port associated with it; that other channel (i.e. not the one used for the Primary Host PC serial communication) on the FT4232HQ is reserved for the PC to communicate with the Platform MCU (and then the Platform MCU communicates with the rest of the system over I2C).
As for communicating with the Platform MCU itself over it's COM port, you will need to configure the serial terminal to 115200 baud, 8 bits, even parity, 1 stop bit, with a line feed following each command (described further in it's section of the Reference Manual, https://digilent.com/reference/programmable-logic/genesys-zu/reference-manual#platform_mcu).
As for the FTDI page in the schematic, Digilent has made the choice to not reveal this page of the schematic. You are not the only one disappointed with this of course, but it is what it is.
Let me know if you have any questions.
Thanks,
JColvin

Hi @R.Dinkel,
I would recommend reaching out to Keithley to find out this information; Digilent does not have any experience with this product that you mentioned.
Thanks,
JColvin

Hi @Mike C,
I reached out to the engineer most familiar with the Adept software and they let me know the JTAG UART communication you are describing is not possible to do with Adept, or at least they were not aware of a way to access the bscan registers (which is what the MDM JTAG UART is using) outside of the Xilinx toolchain.
What I would probably recommend doing as an alternate option since I presume you don't have existing UART access otherwise would be to implement something like an AXI UartLite IP and route the Rx and Tx to some external pins and using something like the Pmod USBUART (https://digilent.com/reference/pmod/pmodusbuart/start) so you can then receive serial messages over something like PuTTY or TeraTerm.
Thanks,
JColvin

Hi JColvin,
 
I made some twisted pairs as shown on Digilent site and glitches are gone.

Best regards,
 
David

Hi @brahmadev,
No license is required to generate bitstreams for the FPGA present on Digilent's Arty A7. You can verify this for yourself by seeing what device groups are listed as supported in the Vivado ML Standard Edition column in Xilinx's UG973: https://docs.xilinx.com/r/en-US/ug973-vivado-release-notes-install-license/Supported-Devices.
Thanks,
JColvin

https://fpgaer.tech/?p=465
Magellan HW monitor for Basys 3 board
Access register bank for reading/writing via JTAG to AXI adapter.
Can also monitor register values via the board seven-segment display (register address is selected through SW0-3)