JColvin

Hi @CoraZ7Fan,
I got a bit of unexpected spare time; the Statement of Volatility is available in the Additional Resources section of the Cora Z7 Resource Center: https://digilent.com/reference/programmable-logic/cora-z7/start#additional_resources.
Let me know if you have any questions.
Thanks,
JColvin

Hi @Rachel,
Edit: Looks like Attila beat me to it, but I'll post my response anyways.
pydwf was developed by @reddish, so I will leave it to them for commentary on the compatibility.
The Analog Discovery 2 could have up to 16 KiS (16384 samples) per channel depending on the device configuration selected within the WaveForms Device Manager. The Analog Discovery 3 on the other hand doubles this with up to 32 KiS (32768 samples) per channel, again depending on the selection within the WaveForms Device Manager (The oscilloscope in particular on the Analog Discovery 3 can have up to 64 KiS if you select the 32 KiS configuration within the WaveForms Device Manager and then disable/uncheck one of the channels so that it's buffer is instead allocated to the remaining, enabled channel).
You can learn more about the specific buffer sizes for the devices in the Analog Discovery 3 Specifications document: https://digilent.com/reference/test-and-measurement/analog-discovery-3/specifications.
Yes, both the AD2 and AD3 are compatible with WaveForms new Select+Dual mode where two identical devices (two AD2s or two AD3s for example) can have their two trigger lines connected and then have a unified view within WaveForms (for 4 analog inputs, 4 analog outputs, and 32 digital channels). The Analog Discovery 2 will only be software timed and will experience some drift in synchronization, but the Analog Discovery 3 with it's larger FPGA supports hardware timing for much tighter synchronization between the two devices.
As both trigger lines are used in this feature, it is only possible to concatenate two devices together. You could open up a second instance of WaveForms to control additional devices, but there is no way to neatly synchronize that instance with the Select+Dual at this point in time.
You would most likely be interested in learning about the Analog Discovery Pro 3450 then: https://digilent.com/reference/test-and-measurement/analog-discovery-pro-3x50/start. It has 4 analog inputs and 2 analog outputs at 14-bit resolution and 16 digital channels with 1.2 V to 3.3 V CMOS logic (5 V input tolerant), two external triggers, as well as on-board DDR memory for a much larger buffer for the analog and digital inputs (128 MiS total for the analog inputs and 64 MiS for the digital inputs). It also offers an embedded Linux mode so it can be used as a standalone device without needing to be tethered to a host computer running WaveForms in order to operate.
Digilent also has a slightly different Analog Discovery 5250 (which is based on NI's VB8012), https://digilent.com/reference/test-and-measurement/analog-discovery-pro-5250/start, which offers higher bandwidth and sample rates (up to 1 GS/s and 100 MHz bandwidth on the oscilloscope channels and 1 GS/s Logic Analyzer) and has a DMM, but does not have other features such as a Pattern Generator.
Let us know if you have any questions.
Thanks,
JColvin

Hi @egonotto,
What settings do you have the Analog Discovery 3 set to / what are you attempting to record? For best results, make sure you have chosen the configuration that allocates the most buffer to the particular instrument of interest (such as Configuration 2 for the Oscilloscope or Configuration 4 or 5 for the Logic Analyzer). It should be able to reach up to 10 MS/s for a single channel when recording to host Computer RAM (changing the Mode dropdown from Repeated to Record) and up to 5 MS/s when Recording directly to file (Control -> Record to file or the "Rec." option next to Export).
Let us know if you have any questions.
Thanks,
JColvin
 

Hi @Goubinda Sarkar,
You can find the code from the Analog Devices repository on an older branch
https://github.com/analogdevicesinc/no-OS/tree/2018_R1/Pmods/PmodAD4

Hi @bcoghlan,
I have not heard of any plans to update / refresh the Digital Discovery at this point in time, though I personally don't doubt that such an effort is under consideration (even if Xilinx keeps extending the lifespan of how long they will produce Spartan 6 chips). When Digilent does have something to share, we will be sure to announce it.
For what it's worth, while the Analog Discovery 2 is no longer going to be produced (i.e. once it's out of stock it's gone), I have not heard any such plans to discontinue the Digital Discovery.
Thanks,
JColvin
P.S. Technically speaking the Analog Discovery 3 still uses the Spartan chip, it's just now a Spartan 7 rather than a Spartan 6.

After Xilinx themselves published tools and reference schematics which allow everyone to create such a tool should they want, it makes no sense for them to continue hiding it. 

Hi @pastucky,
D1 is an onsemi NSQA6V8AW5T2G.
Thanks,
JColvin

To my knowledge Digilent has never published a design that changes the Nexys Video Vadj voltage.
According to the boards' reference manual, if VADJ_EN is low, then the regulator providing Vadj is disabled, so 0V. The reference manual is in error about any "default" value for Vadj. Once VADJ_EN is asserted to a logic high state, the regulator drives Vadj to be 1.2V, 1.8V. 2.5V or 3.3V according to the state of the 2 SET_VADJ output pins. There will be a delay before Vadj becomes stable. If you use the high impedance PULL_UP constraint on all of the output pins that control that regulator you will get Vadj = 3.3V, maybe.
According to the reference manual you should not change the state of the SET_VADJ outputs while VADJ_EN is asserted.
It's possible to assert pin outputs to  default value that isn't 0. If you don't want to do that then your design has to bring up the Vadj power supply explicitly.
One way to do this is to have an up counter control these pins after configuration.
  -- a counter to set the Vadj voltage
  -- Need to use a clock that is always available and isn't from the FMC connector !!!
  vadj_count_proc : process(clk100,areset)
  begin
    if areset = '1' then
      vcnt <= (others => '0');
    elsif (rising_edge(clk100)) then
      if vcnt < X"FFFFFFFF" then -- important to stop counting before overflow...
        vcnt <= vcnt + 1;
      end if;  
    end if;                                                                       
  end process vadj_count_proc;     

  -- To change Vadj we need to do this:
  --  VADJ_EN   <= '0'  disable the regulator
  --  SET_VADJ  <= sets the Vadj voltage: {0,1,2,3} --> {1.2V, 1.8V, 2.5V, 3.3V}
  --  VADJ_EN   <= '1'  enable the regulator
  --  VADJ_EN = '1' and SET_VADJ = "00" when the FPGA is not driving these signals
  -- We need Vadj to be 2.5V so                    
  set_vadj        <= "10" when vcnt > X"00FFFFFF" else (others => 'Z'); -- set to 2.5V 167 ms after configuration
  vadj_en         <= '1'  when vcnt > X"01FFFFFF" else '0';             -- enable the Vadj control 336 ms after configuration
Some designs using an FMC mezznine card may bot want to reset vcnt after configuration as shown above.T
This user selectable Vadj arrangement was poorly thought out. I can't think of case where one would want to change Vadj after configuration. The Genesys2 that followed the Nexys Video has a more practical and safer power supply design.
As for "enabling FMC pins", I assume that this is a translate into English artifact. The FPGA IO connected to the FMC connector are always enabled if your design provides proper location constraints and the toplevel entity of your design includes them on the IO port. The problem is making sure that the voltage powering the Vadj banks have compatible IOSTANDARD assignments as the logic on the FMC carrier board. That's the potential problem with how the Nexys Video board sets Vadj.                                              

Hi @Satian Anantapanyakul
It depends on the cabling.
Notice the columns with and without BNC.

Just wanted to share here, in case someone else faced the same issues as me. Realised that there is no need to use a Raspberry Pi 4 environment for Docker, within Raspberry Pi 4 itself. It is Docker, so swapped to Debian Buster, for arm-based system instead, and the problem is solved.
https://hub.docker.com/layers/library/debian/buster/images/sha256-a067a9e8b39d5f19659b3bc9fd4348f6319afabd0d6ba1fe3b43df108926ea92?context=explore

Hi @alpanth,
Attila (who created this material) is out of the office until next week to give an official answer, but I believe this is intentional based on the WaveForms SDK Reference Manual (available in the WaveForms installation folder on your computer); the start of section 5, Analog In (Oscilloscope) describes the Analog In instrument states and Running and Trig'd be described in the same state, which makes sense because once a trigger condition is met the acquisition would then be running.

Let me know if you have any questions about this.
Thanks,
JColvin

Hi @AndreiNorocea,
Yes, I would encourage you to reach out to Farnell now to try to get a replacement for the BNC probes. Please feel free to link to this thread as evidence of having worked with Digilent staff on this issue.
Thanks,
JColvin

Hi @t0bi,
There should be no issue running the Pmod RS485 at 5 V; the datasheet for the embedded module (https://www.analog.com/media/en/technical-documentation/data-sheets/ADM2582E_2587E.pdf) even uses Vcc at 5 V (unless otherwise noted) in its Specifications table.
3.3 V is listed in the Reference Manual since all of the Digilent system boards with Pmod Host Ports operate with 3.3 V logic, but there isn't really any difference between operating at either of the two voltages from a pragmatic functionality standpoint.
If you wanted to be technical about it, the Typical Performance Characteristics graphs in the Analog Devices datasheet indicate that operating at 5 V consumes less current than when operating at 3.3 V (based on Figure 3 and Figure 4), but that's at the cost of operating at ~100 mW higher (at least for when I looked at 20 degrees C with an RL of 120 Ohms). Whether that is something you are concerned about in your system I do not know.
Thanks,
JColvin

Hi @Agustinus,
@asmi and @zygot are correct in that we will need some more details about the types of sensors that you have before any effective answer can be provided. Are these sensors all communicating simultaneously at 96 kHz? Individually addressed like different nodes on an I2C daisy chain that collect data at 96 kHz? Something else entirely?
It would also be very helpful to know the number of individual data inputs and outputs each sensors needs as I would hazard a guess that each sensor is not a one-wire device so you would need much more than 128 spare I/O pins which most of the Digilent and MCC boards (including the Arty A7 100T) do not have available.
Thanks,
JColvin
 
@zzzhhh I am not sure why you brought up the book reference on creating a digital oscilloscope or the Getting Started with Microblaze Servers tutorial, as neither of those things seem to be relevant to the topic at hand of integrating over 100 sensors into a system. I would ask in the interest of clarity and helping the original poster to only address the question at hand. I spoke with @artvvb a bit earlier today and learned that they are still looking into your question on the topic here: https://forum.digilent.com/topic/25583-to-digilent-employees-is-there-any-chance-to-update-the-tutorial-arty-getting-started-with-microblaze-servers/; currently they believe the issue might be due to same changes in DDR clocking, but they are still debugging the issue alongside the myriad of other tasks that they have on their plate as a Digilent employee, though they hope to find a solution in a reasonable time frame.
 

Hi @FPGA4Life,
You're correct that the Verilog design should work between the Nexy A7 and the Basys 3 for the same external module with only changes needed in the .xdc. Since you already checked the address pins match (which they do) this just leaves the physical connection between the module and the Basys 3.
In this case, (I don't see your code or physical setup) my guess is that the difference is that you are missing the pull-up resistors (which are included on the Nexys A7 circuitry, but not on the Pmod itself). To implement pull-ups on the Basys 3, you would model the .xdc pins as follows (the pins I'm posting below are almost certainly not the pins you are using on header JC):
Let me know if you have any questions or if this change does not work (I'm guessing this is the root of the problem rather than the 7-segment display being the issue) so we can debug further.
Thanks,
JColvin

Hi @CTS,
I have reached out to the appropriate contacts at Digilent about your query; I will reply back when I learn more information.
Thanks,
JColvin
 

Hi @reddish
I had a similar observation a few days ago and got the following response:
"...We're also working on ways to make this process easier for customers.  For example, soon, customers that are already signed into their Digilent account will not see this form at all and will be taken directly to a download page."
You can also download the update directly from the app:

Amen. How many times have I posted the same thought? The AD product support is excellent beyond all expectations, why do stupid things to engender consternation among your customer base that has no benefit to anyone? Please resist old habits and make life easier for your customers... and yourselves in the process.

Hi @Phil06,
You can certainly use jumper cables / wires to have the JTAG HS3 connect to a 6-pin JTAG interface instead, but it will be a bit finicky as asmi indicated.
Otherwise, it may be worth it to ask the Sales team if you can return/exchange the JTAG HS3 for a JTAG HS2 via the Sales and Order Support form available here: https://digilent.com/shop/shipping-returns/#return-policy (I have no access to any sales or shipping systems).
The main technical difference between the JTAG HS3 and the HS2 is that the HS2 does not have a PS_SRST pin to be able to reset the processor on Zynq devices during debugging operation, so as long as that is not an issue, there should be no problem to switch over to a JTAG HS2.
Thanks,
JColvin

JTAG pins can't be included into XDC file because they are dedicated function pins, and can't be used for anything except JTAG.
Which is just stupid now considering Xilinx has finally published a tool which can program FTDI's EEPROM to function just like Digilent's programmer/debugger, but it would only cost about $5 in parts instead of $50+ which Digilent charges for it's solution.

While programming, I recognized that there is a difference between the WaveForms SDK Reference Manual and the dwf.cs file provided in the samples.
Lines 23 - 26 are:
public const int devidADP3X50 = 6; public const int devidEclypse = 6; public const int devidADP5250 = 6; public const int devidDPS3340 = 6; I think they should be:
public const int devidADP3X50 = 6; public const int devidEclypse = 7; // Not mentioned in the reference manual public const int devidADP5250 = 8; public const int devidDPS3340 = 9; According to reference manual section 3 "Device Enumeration".
Best regards
oeser

Hi @AlexanderGDean,
I am not certain of the exact answer (maybe Attila will be able to offer some more details once it is regular working hours in his European timezone).
I know that based on Section 6.3 of the Hardware Design Guide, https://wiki.digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide#power_supplies_and_control, that the particular IC in question for the User Supplies has low voltage drop reverse supply protection as well as analog undervoltage and overvoltage protection though I'm not readily able to determine the details of what those two line items mean from the related sections and equations of the guide, but perhaps you might find some insight from the listed information.
Thanks,
JColvin

HI @mahinay
I would recommend contacting Xilinx to receive an accurate answer to your question as they are the creators of this IP and Digilent does not have any hardware products that use this system.
Thanks,
JColvin

Hi @zzzhhh,
There is not a Verilog version, but the Out-of-box demo is the GPIO demo which contains the VHDL sources. That material is available here: https://digilent.com/reference/programmable-logic/basys-3/demos/gpio.
Thanks,
JColvin

Hi @Lihua,
The JTAG-USB Cable (SKU 250-003) approximately 153 cm in length including the embedded connectors on each end. Excluding the connectors, the cable length is 144 cm.
The JTAG HS3 (SKU 410-299) consists of both actual HS3 module and a microUSB cable. The JTAG HS3 module itself is 3.2 cm in length. The included USB Cable is 1.2 meters in length.
Thanks,
JColvin