JColvin

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  1. Like
    JColvin reacted to Larry Standage in Difference between original UC32 (Retired) #410-254-RET and UC32 REV B #410-254   
    Physically, nothing is different. It was a labeling thing when the chipKIT logo was removed.
  2. Like
    JColvin reacted to xc6lx45 in hard working FPGA...   
    1920x1080, 60 FPS, every pixel is recalculated for each new frame. Standard Julia set with 29 iterations limit.
    100 % DSP utilization on a CMOD A7 (35); 9e9 multiplications per second in 25 bits still running on USB power if getting a little warm.
    Probably more to come later ... stay tuned ūüôā
     
     
  3. Like
    JColvin got a reaction from tip.can19 in What is CYINIT and it's difference with CI in CARRY4 block?   
    Hi @tip.can19,
    The CYINIT pin appears to be an initialization bit, presumably to have the IP block to prepare itself for incoming data. It looks like this Xilinx thread addresses this in more detail.
    Thanks,
    JColvin
  4. Like
    JColvin got a reaction from V94 in Required reference manual for embedded vision demo   
    Hi @V94,
    If you are just trying to run the Embedded Vision Demo to confirm it works, all you need to do is copy the BOOT.bin file (located in the bin folder of the Embedded Vision Demo source files that are linked within the PDF you attached) onto a microSD card.
    If you are wanting to view the project files, you would need to open up Xilinx SDK 2017.4 (opening Vivado 2017.4 is only necessary if you want to make changes to the block design), choose the Workspace location (I choose the sdk folder within the Embedded Vision Demo folder), and then go to File -> Import -> General -> Existing Projects into Workspace, and then click Next. The first radio button option where it says "Select root directory" will have a Browse button; click Browse and select the same sdk folder within the Embedded Vision Demo folder. 5 checked projects should appear in the white box area consisting of the fsbl, fsbl_bsp, pcam_vdma_hdmi, pcam_vdma_hdmi_bsp, and the system_wrapper_hw_platform_0. If all 5 of those are checked, go ahead and click Finish. You will then be able to see the source code and make changes to the project from there.
    Let me know if you have any questions.
    Thanks,
    JColvin
  5. Like
    JColvin got a reaction from D4ILYD0SE in MPLab Chipkit Import Issues   
    Hi @D4ILYD0SE,
    I haven't used this importer before (Digilent works with their own Digilent Core now), but I tested nearly the same setup (exception is that I have MPLAB X 3.60 rather than a newer version, all other pieces the same version as you), but encountered the same error. The way that project is copied to a different location so that can be imported seems strange to me since I would expect that it needs more information to import, but that is what the tutorial states, so I followed it.
    My guess now is that either the newer chipKIT Cores are no longer compatible with the importer tool that has a 2017 date (perhaps unlikely based on my limited knowledge of how cores are designed, but I don't know this for certain) or the Arduino IDE had something changed.
    If I get a successful import on one of these older revisions, I'll let you know.
    Thanks,
    JColvin
  6. Like
    JColvin got a reaction from Takashi "The Yaka mein" in Power supply 6003-300-000   
    Hi @Takashi "The Yaka mein",
    I apologize for the delay. I am not certain why that particular power supply is not included for the Japan export version of the kit that Xilinx makes. Your guess that it could be a certification issue would make sense, though I do not know this for certain since that particular power supply isn't sold directly on our website as per this forum thread here. I will ask and find out if somebody at Digilent happens to know the reason the power supply would be excluded from the Japan export version, though it may be better to reach out to Xilinx as they are the ones who made that choice for their kit.
    Thanks,
    JColvin
  7. Like
    JColvin got a reaction from andresb in PMODs - Spec 1.2.0   
    Hi @andresb,
    I apologize for the delay.
    The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf.
    Let me know if you have any questions about this.
    Thanks,
    JColvin
  8. Like
    JColvin reacted to Commanderfranz in WaveForms Live Update: New Features!!   
    Hey All,
    We recently posted a new version of WaveForms Live which ads some new features. This blog post lists all the changes in the update. 
  9. Like
    JColvin reacted to D@n in Problems FFT IP CORE v 9.0   
    @Kenny,
    If you are an FPGA beginner, then ... I would start somewhere else.  I would recommend starting by learning how to debug FPGA designs.
    The problem with FPGA development is that, unlike software, you have little to no insight into what's going on within the FPGA.  There are a couple keys to success:
    Being able to insure your design works as intended before placing it onto the FPGA.  Simulation and formal methods work wonders for this task.  Unlike debugging on hardware, both of these approaches to debugging offer you the ability to investigate every wire/signal/connection within your design for bugs.  If you are unfamiliar with these tools, then I would recommend my own tutorial on the topic. Being able to debug your design once it gets to hardware.  This should be a last resort since its so painful to do, but it is a needed resort.  To do this, it helps to be able to give the hardware commands and see responses.  It helps to be able to get traces from within the design showing how it is (or isn't) working.  I discuss this sort of thing at length on my blog under the topic of the "debugging bus (links to articles here)", although others have used Xilinx's ILA + MicroBlaze for some of these tasks. Either way, welcome to the journey!
    Dan
  10. Like
    JColvin got a reaction from Takashi "The Yaka mein" in Digilent Part # for Xilinx Eval Board Power Supply   
    Hi @AvnetRH,
    I haven't ever worked with this particular power supply so I do not know if this is true, but there is a possibility that the Xilinx Development boards may refer to development boards that Digilent sells (such as the Arty). After getting some more information from our sales team (since the part is not directly available on our website), it seems you will need to email our sales team, sales at digilentinc dot com, to be able to request that specific power supply.
    Thank you,
    JColvin
  11. Like
    JColvin got a reaction from sgrobler in Openlogger Wifi - seems to have stopped working since firmware 1.3.0   
    Hi @sgrobler,
    I am able to successfully connect to my phones WiFi hotspot on firmware 1.3.0. I get the same message pop-up as you regarding the firmware update required, but I click the "OK" option and then select the Instrument Panel where-upon am I greeted with the same message, choose OK again, and then I am brought to the Instrument Panel where I am able to successfully run the OpenLogger.
    I do agree though that the pop-up message should not be occurring though. I have reached to @AndrewHolzer to help address this.
    Thank you for the feedback,
    JColvin
  12. Like
    JColvin got a reaction from greengun in Can Arty Z7 handle 4k60p hdmi?   
    Hi @greengun,
    No, the transceiver pins on the Arty A7 FPGA (a XC7A35TICSG324-1L FPGA) are no broken out. As per Xilinx UG475 (page 41), the HR I/O bank 16 is only partially bonded out, but as per the Arty A7 schematic, the HR I/O pins on bank 16 are not used.
    Thanks,
    JColvin
  13. Like
    JColvin reacted to Bianca in Evaluation boards   
    Hi @mariushvn,
    There is no difference between them. The original was Artix-7 35T Arty FPGA Evaluation Kit and then we re-branded the Arty category by sticking to the same form factor but with different FPGAs (artix, spartan, zynq). To make sure there won't be confusion between the products, the original Arty is called now Arty A7. The new thing is that it can be found now also with a bigger FPGA, the 100T not only with the 35T how it was the original. 
     
    Best regards,
    Bianca
  14. Like
    JColvin reacted to Bianca in How to restore FT2232 EEPROM back to factory settings?   
    Hi @svet-am,
    This solution works just for the Digilent boards. Please contact Xilinx for support in order to fix your KCU1500 board.
    Best regards,
    Bianca
  15. Like
    JColvin got a reaction from Takashi "The Yaka mein" in Pmod RS485 size   
    Hi @Takashi "The Yaka mein",
    We have a 3D model of the Pmod RS485 available in it's Resource Center on the right hand side under Documentation.
    Let me know if you have any questions.
    Thanks,
    JColvin
  16. Like
    JColvin got a reaction from yildizberat in WHY VGA PMOD NOT WORKING ON MY ZYBO-Z7-10 BOARD (SOLVED)   
    That's alright; I'm glad you were able to get it working!
  17. Like
    JColvin got a reaction from yildizberat in WHY VGA PMOD NOT WORKING ON MY ZYBO-Z7-10 BOARD (SOLVED)   
    Hi @yildizberat,
    What version of Vivado are you using and what monitor resolution do you have? I used the 2018.2 release available here: https://github.com/Digilent/Zybo-Z7-10-Pmod-VGA/releases successfully. I did end up regenerating the bitstream to get it to work successfully though.
    Thanks,
    JColvin
  18. Like
    JColvin got a reaction from satvik in Vivado2015.4 is not reading cora z7-07s board file   
    Hi @satvik,
    I believe you can get all of the functionality from the WebPACK version of Vivado (most of us here at Digilent use the WebPACK for most of the work we do). There may be some IPs that require an external license that is not included with WebPACK (or the Design or System edition) versions of Vivado, such as more complex Ethernet or USB IPs from Xilinx. But you would be able to implement a Pmod WiFi with the Cora board; we have an example using the Pmod WiFi with a different Digilent board here as well as a thread on it here and here.
    Thanks,
    JColvin
  19. Like
    JColvin got a reaction from satvik in Vivado2015.4 is not reading cora z7-07s board file   
    Hi @satvik,
    I apologize for the delay. The reason the Cora Z7-07s is not present in Vivado 2015.4 and 2016.1 is because Xilinx had not added those parts to their software. From what I know, the XC7Z007S chip (the SoC present on the Cora board) was not added to the Vivado WebPACK version until 2016.3.
    Otherwise, if you are looking to follow Digilent made examples for the Cora Z7-07s, I would recommend using Vivado 2017.4 or 2018.2 as those are the versions of Vivado that we have made examples for the Cora Z7, which you can find in the Cora Z7's Resource Center.
    Thanks,
    JColvin
  20. Like
    JColvin got a reaction from Tejna in Embedded Linux Question Disclaimer   
    Hello!
    Welcome to the Digilent Forums! All of us here, both Digilent Staff and our incredible community members, are excited to be able to help you out with your project. 
    That being said, we are not the ultimate experts on Embedded Linux. A couple of us have a decent amount of experience, but unfortunately we cannot guarantee that we can identify the issue and have the solution to your problem for your exact distro, drivers, board, and application. We will try to help out the best that we can, but it may take some additional time to provide feedback on any questions that you may have.
    Thanks,
    The Digilent Team
  21. Like
    JColvin reacted to zygot in can bus implementation in fpga (suitable board?)   
    You'll definitely have to order CAN PHY devices unloess you find a board with a PHY already connected to the FPGA.
  22. Like
    JColvin reacted to vicentiu in Reading I2C via script displays wrong data   
    FYI, Attila is on vacation returning on Oct. 9th.
  23. Like
    JColvin got a reaction from P. Fiery in Script to enable or disable FFT display in scope.   
    Hi @P. Fiery,
    I have tagged the engineer, @attila, who will be best able to address your question as they are much more familiar with the WaveForms software.
    Thanks,
    JColvin
  24. Like
    JColvin got a reaction from Franky32 in How to restore FT2232 EEPROM back to factory settings?   
    Hi @jfranz-argo, @kharoonian, and @Franky32,
    I apologize for the delay. I have sent each of you a PM about this.
    Thanks,
    JColvin
    P.S. to other readers, be sure not have Digilent boards attached when you are reprogramming other FTDI devices. A long list of users will tell you it's an easy mistake to accidentally select the wrong device.
  25. Like
    JColvin reacted to Lesiastas in Understanding the captured sample with FDwfDigitalInStatusData   
    Hi @attila
    Thank you again for all the support you've provided me for the past weeks. I am now capable of receiving more than 409 characters using the Wrapper I created base from your example. It uses the Record acquisition mode and I set the buffer size to 3 million for now. I'll increase it when the need arises.
    I used 1 UART controller and branched out its Tx pin to 2 DIO pins of the AD2 (DIO #0 & 1).
    I transmitted 500 characters: 
    (If Record mode is not the acquisition mode, the received result will be blank)

    For DIO # 0, it received:

    with a length of: 
    For DIO #1, it received:

    with a length of: 
    I could not have done it without your guidance, thank you again and more power to you and Digilent
    Best regards,
    Lesiastas