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  1. Like
    JColvin reacted to Robot in compiling for arduino board   
    Hi J. Colvin. Thank you for that information. I am delighted to say it worked. I cleared the two libraries and started everything the sketch on a new version and then downloaded the libraries again, loaded the sketch manually as it is a short program and it is working fine now. Thank you again for directing me where to look for the solution.
  2. Like
    JColvin got a reaction from rober423 in Academic Pricing   
    Hi @rober423,
    Are you still encountering this error? I know one thing that I had to do in the past was disable my ad-block since that was preventing the page from properly loading.
    Thank you,
  3. Like
    JColvin got a reaction from chcollin in Storing Atlys PLB project to SPI/Flash   
    Hi @chcollin,
    Re-reading the tutorial, the bootloader that is provided is intended to reader from the SPI flash via the Xilinx In-System Flash library (as opposed to the default provided by SDK that uses parallel NOR Flash) specifically for the flash on the Spartan-6 LX9 MicroBoard.
    Based on Table 5-5 (Spartan-6 FPGA Bitstream Length) in the corresponding User Guide, the default bitstream length is much larger for the LX45 device (11,939,296 bits), corresponding to 1.4574 MB. Looking at the flash used on the Atlys (a N25Q128 Numonyx chip which has 64 KByte sectors), this would use the first 23 sectors, leaving 233 sectors (~14,900 KBytes) for the application. It is also possible to compress the bitstream to have it use less resources, though I don't know how much it would get compressed. Extrapolating from the Avnet tutorial, the offset to choose in the blconfig.h file (create boot loader application, step 9) should be 0x170000.
    With regards to the flash family, I think you would want to choose the 5th one (Spansion) based on the Xilinx documentation for xilisf, since that Spansion option also apparently counts for Micron (and I understand the Numonyx chips are now owned by Micron), though I am uncertain about this since the tutorial I linked you to states that Micron devices have the same control set as STM (option 3).
    I'm not certain on the XPAR_SPI_FLASH_DEVICE_ID bit; everything that I have found leaves this value unchanged. I'll keep looking and let you know if I find something.
  4. Like
    JColvin got a reaction from chcollin in Storing Atlys PLB project to SPI/Flash   
    Sweet, I'm glad to hear the design has been exported; I hope the bootloader side of things in SDK works as well.
  5. Like
    JColvin reacted to chcollin in Storing Atlys PLB project to SPI/Flash   
    Update 1
    I managed to add xps_spi core to HDMI_DEMO project and export design ūüėÄ
    As I didn't know how to configure it, I started a new XPS project from scratch using BSB wizard and Atlys_PLB_BSB_Support files to retrieve those needed information.
    Then, back to HDMI_DEMO project, I configured my new xps_spi core as follows :
    Added those lines to system.ucf :
    Net xps_spi_0_SCK_pin LOC=R15  |  IOSTANDARD=LVCMOS33;
    Net xps_spi_0_MISO_pin LOC=R13  |  IOSTANDARD=LVCMOS33;
    Net xps_spi_0_MOSI_pin LOC=T13  |  IOSTANDARD=LVCMOS33;
    Connected xps_spi core ports to those.
    Finaly, configured xps_spi core as indicated in screenshots.
    Export was successful. I'll do the SDK part tomorrow.
    Thanks again @JColvin

  6. Like
    JColvin reacted to zygot in Vitis   
    I really appreciate your help. I suspect that I could have had more success by choosing the 'Hello' Application but why bother? I will pursue a Zedboard Vitis project and if it's interesting will post it. It'll be a tertiary level enterprise though.
    At this point I've concluded that Vitis and therefore Vivado 2019.2 or later are 'not ready for prime time'. Actually Vivado 2016.2 on WIn7 is my main HDL Xilinx toolset 'main squeeze' and except for a few idiosyncrasies gets the job done. At least I'm familiar with it's quirks. I still can't figure out why implementing a memory viewer in Vivado Simulator is so hard... Quartus has had a hardware memory tool for decades.... ISE ISIM can do it.
    A lot of my angst has to do with the knowledge that the Win7 box will die someday and I really haven't found a suitable successor yet. IF only Centos 6 were based on a slightly later Kernel it would be one OS to last (almost) forever.
  7. Like
    JColvin reacted to hamster in CMOD A7 Audio board...   
    The last of the parts came in and the new board is up and running.
    Here's the old and new boards side by side, and spectrum of a 10kHz test tone going from the ADC, through the FPGA and then DAC (top = new board, middle = old board, bottom = no board in the loop.
    The additional work I did on grounding on the PCB has paid off, with a very good noise floor - better than I can measure with the tools I have to hand.

  8. Like
    JColvin got a reaction from Cristian.Fatu in Storing Atlys PLB project to SPI/Flash   
    Hi @chcollin,
    I don't have EDK available to me to be able to test the Atlys HDMI demo (nor did I directly find answers to the questions you put in quotes), but I was able to locate a reference design  for a Spartan 6 chip that creates a MicroBlaze SPI flash bootloader that uses PLB here: https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-s6mb-lx9-g-3074457345628965461?aka_re=1. The Reference Design is called "EDK 12.4 Tutorials Creating a MicroBlzae SPI Flash Bootloader for AES-S6MB-LX9-G". I have attached the pdf tutorial that walks through the process that came with that download for convenience.
    Let me know if you have any questions about this (or if this was not what you were looking for in your situation).
  9. Like
    JColvin got a reaction from fmilburn in Glitch in Output from Wavegen on OpenLogger   
    Hi @fmilburn,
    I have asked some engineers more familiar with WaveFormsLive about this.
  10. Like
    JColvin reacted to hamster in RISC-V RV32I CPU/controller   
    I've just posted my holiday project to Github - Rudi-RV32I - https://github.com/hamsternz/Rudi-RV32I
    It is a 32-bit CPU, memory and peripherals for a simple RISC-V microcontroller-sized system for use in an FPGA.
    A very compact implementation and can use under 750 LUTs and as little as two block RAMs -  < 10% of an Artix-7 15T.
    All instructions can run in a single cycle, at around 50MHz to 75MHz. Actual performance currently depends on the complexity of system bus.
    It has full support for the RISC-V RV32I instructions, and has supporting files that allow you to use the RISC-V GNU toolchain (i.e. standard GCC C compiler) to compile programs and run them on your FPGA board. 
    Here is an example of the sort of code I'm running on it - a simple echo test:, that counts characters on the GPIO port that I have connected to the LEDs.
    // These match the address of the peripherals on the system bus. volatile char *serial_tx = (char *)0xE0000000; volatile char *serial_tx_full = (char *)0xE0000004; volatile char *serial_rx = (char *)0xE0000008; volatile char *serial_rx_empty = (char *)0xE000000C; volatile int *gpio_value = (int *)0xE0000010; volatile int *gpio_direction = (int *)0xE0000014; int getchar(void) { // Wait until status is zero while(*serial_rx_empty) { } // Output character return *serial_rx; } int putchar(int c) { // Wait until status is zero while(*serial_tx_full) { } // Output character *serial_tx = c; return c; } int puts(char *s) { int n = 0; while(*s) { putchar(*s); s++; n++; } return n; } int test_program(void) { puts("System restart\r\n"); /* Run a serial port echo */ *gpio_direction = 0xFFFF; while(1) { putchar(getchar()); *gpio_value = *gpio_value + 1; } return 0; } As it doesn't have interrupts it isn't really a general purpose CPU, but somebody might find it useful for command and control of a larger FPGA project (converting button presses or serial data into control signals). It is released under the MIT license, so you can do pretty much whatever you want with it.
    Oh, all resources are inferred, so it is easily ported to different vendor FPGAs (unlike vendor IP controllers)
  11. Like
    JColvin reacted to D@n in write and read data with DDR3 SDRAM Arty-7-35T   
    The .prj file @JColvin refers to is an XML (i.e. text) file.  I was able to use it to create this UCF file.
    That's going to be the least of your problems.  See my answers in the other thread for more of what you'll need to deal with.
  12. Like
    JColvin reacted to xc6lx45 in hard working FPGA...   
    Happy new year
  13. Like
    JColvin got a reaction from voltagesurge in high speed ADC aquisition   
    Hi @voltagesurge,
    I'm not certain when it will be updated (I thought it would've been done yesterday), but I was informed that WaveFormsLive will not be taken down at any point during the update process. I'll let you know when I learn that it becomes updated.
  14. Like
    JColvin got a reaction from voltagesurge in high speed ADC aquisition   
    Hi @voltagesurge,
    I confirmed that 500 kS/s is the accurate logging rate and that it is a bug in WaveFormsLive, so we will make sure it gets updated.
    We don't have nice list of SD cards that we recommend, though we have had success with San Disk cards. In general though I would go with a class 10 card.
    Let me know if you have any questions about this.
  15. Like
    JColvin got a reaction from voltagesurge in high speed ADC aquisition   
    Hi @voltagesurge,
    My understanding is that it should be 500 kS/s for the SD card; I suspect this is an error on the WaveFormsLive side of things, though I have asked @AndrewHolzer for clarification on this.
  16. Like
    JColvin got a reaction from voltagesurge in tutorial for beginners to export openlogger to .csv   
    This is a repost of the material from another one of the Digilent engineers:

  17. Like
    JColvin got a reaction from voltagesurge in high speed ADC aquisition   
    Hi @voltagesurge,
    For the OpenLogger, getting it to log to the SD card is as straightforward as setting the "Log to" dropdown setting on WaveFormsLive.com to have it log to SD card. The SD card will need to be 32 GB since that is the largest that the FAT32 format is compatible with, so a 64 GB card will not work as it will be in a different format. When you add channels to be logged on the OpenLogger (as explained in this tutorial, https://reference.digilentinc.com/learn/instrumentation/tutorials/openlogger/datalogger) the sample rate automatically adjusts. With 8 channels, the sample rate will be 62.50 kS/s, and can be decreased to a lower sample rate if that is more appropriate for your system.
    As for logging to an SD card via a different microcontroller, the process will depend; there is an SD library built into the Arduino IDE, but unlike the OpenLogger, it will not be logging analog data to the SD card in the same way with regards to logging data as the SD card as analog data is collected.
    With regards to turning the OpenLogger on and off, that will not be so easy to do. There is not a built in way to trigger the OpenLogger to reset itself (or send a signal out on a GPIO pin to the reset pin after 20 seconds), so you would need an external system (such as another microcontroller) to send this signal. But this would overall make the system less portable.
    Let me know if you have any questions about this.
  18. Like
    JColvin reacted to Larry Standage in Difference between original UC32 (Retired) #410-254-RET and UC32 REV B #410-254   
    Physically, nothing is different. It was a labeling thing when the chipKIT logo was removed.
  19. Like
    JColvin reacted to xc6lx45 in hard working FPGA...   
    1920x1080, 60 FPS, every pixel is recalculated for each new frame. Standard Julia set with 29 iterations limit.
    100 % DSP utilization on a CMOD A7 (35); 9e9 multiplications per second in 25 bits still running on USB power if getting a little warm.
    Probably more to come later ... stay tuned ūüôā
  20. Like
    JColvin got a reaction from tip.can19 in What is CYINIT and it's difference with CI in CARRY4 block?   
    Hi @tip.can19,
    The CYINIT pin appears to be an initialization bit, presumably to have the IP block to prepare itself for incoming data. It looks like this Xilinx thread addresses this in more detail.
  21. Like
    JColvin got a reaction from V94 in Required reference manual for embedded vision demo   
    Hi @V94,
    If you are just trying to run the Embedded Vision Demo to confirm it works, all you need to do is copy the BOOT.bin file (located in the bin folder of the Embedded Vision Demo source files that are linked within the PDF you attached) onto a microSD card.
    If you are wanting to view the project files, you would need to open up Xilinx SDK 2017.4 (opening Vivado 2017.4 is only necessary if you want to make changes to the block design), choose the Workspace location (I choose the sdk folder within the Embedded Vision Demo folder), and then go to File -> Import -> General -> Existing Projects into Workspace, and then click Next. The first radio button option where it says "Select root directory" will have a Browse button; click Browse and select the same sdk folder within the Embedded Vision Demo folder. 5 checked projects should appear in the white box area consisting of the fsbl, fsbl_bsp, pcam_vdma_hdmi, pcam_vdma_hdmi_bsp, and the system_wrapper_hw_platform_0. If all 5 of those are checked, go ahead and click Finish. You will then be able to see the source code and make changes to the project from there.
    Let me know if you have any questions.
  22. Like
    JColvin got a reaction from D4ILYD0SE in MPLab Chipkit Import Issues   
    Hi @D4ILYD0SE,
    I haven't used this importer before (Digilent works with their own Digilent Core now), but I tested nearly the same setup (exception is that I have MPLAB X 3.60 rather than a newer version, all other pieces the same version as you), but encountered the same error. The way that project is copied to a different location so that can be imported seems strange to me since I would expect that it needs more information to import, but that is what the tutorial states, so I followed it.
    My guess now is that either the newer chipKIT Cores are no longer compatible with the importer tool that has a 2017 date (perhaps unlikely based on my limited knowledge of how cores are designed, but I don't know this for certain) or the Arduino IDE had something changed.
    If I get a successful import on one of these older revisions, I'll let you know.
  23. Like
    JColvin got a reaction from Takashi "The Yaka mein" in Power supply 6003-300-000   
    Hi @Takashi "The Yaka mein",
    I apologize for the delay. I am not certain why that particular power supply is not included for the Japan export version of the kit that Xilinx makes. Your guess that it could be a certification issue would make sense, though I do not know this for certain since that particular power supply isn't sold directly on our website as per this forum thread here. I will ask and find out if somebody at Digilent happens to know the reason the power supply would be excluded from the Japan export version, though it may be better to reach out to Xilinx as they are the ones who made that choice for their kit.
  24. Like
    JColvin got a reaction from andresb in PMODs - Spec 1.2.0   
    Hi @andresb,
    I apologize for the delay.
    The best way to determine if they are complaint with specification 1.2.0 is by looking at their respect Resource Center (such as the Pmod AD1). On the right-hand side under Electrical, you will see the Specification version that the Pmod is currently compliant with. The Pmod Interface Specification 1.2.0 is available directly here: https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf.
    Let me know if you have any questions about this.
  25. Like
    JColvin reacted to Commanderfranz in WaveForms Live Update: New Features!!   
    Hey All,
    We recently posted a new version of WaveForms Live which ads some new features. This blog post lists all the changes in the update.