JColvin

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Everything posted by JColvin

  1. Hi @Anju Johnson and @[email protected], I'm not certain why the XDC file is not mentioned at all. I suppose we were presuming that users might have read through other tutorials that do mention it, namely the programming guide, but even then it is a little bit vague... So I will make sure this gets changed, or at the very least points to a tutorial before the project formally starts that explains how to get the XDC file and other setup stuff ready to go. Otherwise, I guess I can recommend checking out step 7 of this guide: https://reference.digilentinc.com/learn/software/tutorials/verilog-project-2/start. Edit: I just learned that installing the board files for this sort of project eliminates the need for an XDC file since it essentially constrains the pins for you. So @jpeyron's question then applies (who told me this info) since they aren't certain why you received this error. Thanks, JColvin
  2. Hi @cvtabc, Agreed about the IPs. I'm not certain what licenses you receive access to; I did a bit of searching for a list of what IPs come with which editions of Vivado but came up empty (but maybe I was searching in the completely wrong location). Some, like the TEMAC I mentioned, apparently won't (from what I've been told from my coworkers) be licensed via the Design Edition, just be able to have a bitstream generated, since apparently the WebPACK Edition will not generate the bitstream for whatever reason. I do not know if such license list exists; the people over on the Xilinx forum might know that answer. Otherwise, it may all be manually asking about individual IPs. Thanks, JColvin
  3. Hi @Clarissa, I'm mostly echoing what @jpeyron said, but from your project requirements, it looks like the Nexys Video that @[email protected] mentioned will likely be your best option if you don't want to use some sort of expansion addon. It'll also have some spare pins available for what you are needing since it has 34 differential pairs on the LPC FMC (which from my understanding you can use as single ended pairs) in addition to the four Pmod ports. If you're fine with the expansion options introducing delays, then your options expand to a much wider range since (from what I can tell) you will then be mostly looking to see if the embedded components you are needing exist on the board and if the FPGA has enough "room" for what you need to do. The Zedboard and Genesys 2 will also work, but have either an entirely different architecture (an SoC on the Zedboard) or are a much larger and fancy FPGA with a HPC FMC in the case of the Genesys 2. Let us know if you have any more questions. Thanks, JColvin
  4. JColvin

    Zedboart to PC via USB

    Hi @CrazyTown, I have moved your question to a different section of the Forum where an engineer better suited to help you will be more likely to see your question. Thanks, JColvin
  5. Hello @Clarissa, I don't know what your project requirements are, but if you're just looking for the 40 pins, you might want to look into the Arty or the Cmod A7. To be fair, these don't have have the same "amount" of FPGA as the Nexys 4 DDR and neither have video capabilities (I don't know if you were needing that in your project), but they do have at least the 40 pins (which I *think* are all available as general purpose pins) and the Arty also has the DDR memory. In terms of an expansion module of some sort for the Nexys 4 DDR to get more I/O pins, there will have to be some delay as you are inevitably going to have to work through another chip with a (de)mux rather than having the signals directly come in on their own dedicated lines to the FPGA, but depending on your design this can potentially be accounted for. Let me know if you have any more questions or details on your project. Thanks, JColvin
  6. Hi @Vinit Shukla, What sort of screen resolution does your display support? I presmed you changed the constants in the provided in the VGA.vhd file as per the settings listed for your particular display on this page? Thanks, JColvin
  7. @Cristobal, Letting you know that I still want to take another look into the Pmod AD5 code, but I haven't managed to find a free moment to dig into it... hooray for having myriad of other tasks to do everyday! I'll let you know what I find when I get the opportunity to check it out. Thanks, JColvin
  8. Hi Assane, I'm not the most familiar with the Adept API, but it looks like you can use the DmgrGetInfo() command with the "dinfoUsrName" parameter value to query the device to find out it's name since I imagine it's something like "HS3". I found these in the DMGR Progammer's Reference Manual on page 2 and the Digilent Adept System Programmers Reference Manual on page 8 that came with the Adept SDK download. Again, I'm not the most familiar with this so I personally can't speak towards the accuracy of this, but I'll make sure you get the help you need. Thanks, JColvin
  9. Hi @HansV, Glad to hear you like it! I was about to post on one of your other threads talking about some of the features that 3.5.4 implemented (like timestamps on the tags) since I learned about the software update today, but clearly you're already aware of it. Definitely big thanks and shoutout to @attila, whom, afaik, implemented all of those changes himself. And to others who might be reading this thread, if you ever wish that the Digilent WaveForms software had some sort of feature, don't be afraid to suggest/request it. To be fair, we won't offer any promises to implement it, but sometimes we (well, @attila) do. Thanks, JColvin
  10. HI @rlopez1024, Unfortunately, we don't have a solution to debug FPGAs remotely. As you noticed, Adept 2 is designed to let you configure an FPGA with a premade bitstream; we haven't really worked a lot on debugging (at least with the Digilent made products designed to enable that). The Digilent plug-in for Xilinx tools is so that our boards and cables can be recognized by the Xilinx tools. I will pass along your suggestion of having Digilent software remotely interface with system boards though. I'm sorry I couldn't be of more help. Thanks, JColvin
  11. JColvin

    Zybo cable drivers

    Hi jacobfeder, Thanks for sharing what you found out! I wouldn't be too embarrassed about it; we've all done it. I usually wonder why my project isn't working only to finally notice that I'm not connected to the pins that I told Vivado that I was using. Thanks, JColvin
  12. Hi @shashi, I don't really know much about HLS, but I did a quick search and it looks like it has something to do with Variable Bound Loops as per this Xilinx forum thread and this Xilinx Answer Record. I don't know what Variable Bound Loops are, but I found the user guide for Vivado 2016.2 HLS (which it looks like you're using) that talks about them on page 314 here, which looks like the analog for what the Xilinx employee referred their customer to. Thanks, JColvin
  13. Hello @cvtabc, You'll have to take this response with a grain of salt considering that we as Digilent are one of those re-sellers that you mentioned, but I'll see if I can give you a helpful response here on the Forum having set aside my webteam hat. All major versions of Vivado that I presume you would be looking into (WebPACK, Design, and System Editions) all support the Vivado Logic Analyzer and various debug IPs such as the Intergrated Logic Analyzer, which as I understand it is Vivado's successor to Chipscope from Xilinx ISE. Considering that Xilinx has not stated any plans to continue to working on ISE and will be primarily focusing on supporting Vivado, I wouldn't be too anxious to get a Chipscope license (although the link you provided to Digikey didn't indicate anything about Chipscope). Similarly, Vivado has its own version of a simulator like ISIM, which all major versions of Vivado include. I don't know what the differences of the simulator, if any, are between the various editions of Vivado. None of us at Digilent have experience with EPICS so we can't speak towards that. However these newer editions of Vivado (2016.1 onward if I'm not mistaken) support HLS (High-Level Synthesis) to allow for C/C++ development in the Vivado environment, although I do not personally know how robust it is, but I suspect it does fairly well for what it is and that Xilinx will support it since it was recently implemented. The SDSoC license would probably be good in this case since it's likely a lot more optimized for writing C/C++ code for an SoC, such as the Zynq chip present on the Zedboard. In terms of IP cores, that is something that the Design Edition Voucher would be good for since it will give you (from my understanding) it will let you generate bitstreams for some of Xilinx's more complex IPs cores such as TEMAC. The TEMAC core isn't included with the Vivado Design edition though (from my understanding) so it would need to be evaluated or licensed separately. Lite ethernet versions from Xilinx do exist though that don't require the Design Edition of Vivado, but are more limited in functionality (although I can't personally speak towards how they are limited/in what way they are different). Those of us here are Digilent aren't familiar with EtherCAT so we can't speak towards that. From your initial description, I presume this work would be lab related as opposed to classroom based teaching material, so I imagine this is less of a "learning/teaching" as opposed to an "implementing" situation, so that'll affect your decision. I guess the thing with vouchers of any kind is that they are node locked (so they only are applied to one system/computer) and are only valid for one year. During that year you can upgrade to newer versions of that particular edition that Xilinx releases at no additional charge, but be unable to do so after that year without re-purchasing access to the edition. After that year is up, you will be able to use whatever edition is installed on that machine more or less indefinitely without restrictions. In the end, it sounds like you'll end up wanting some sort of Vivado edition with good C/C++ support. However, Digilent (I can't speak for Avnet or Xilinx) won't be able to offer a ton of help integrating 3rd party systems into your solution since we don't actively support them. So to me it sounds like you'll either want the SDSoC voucher or the Design Edition voucher, although I don't know what additional IPs the Design Edition enables nor do I know a whole lot about SDSoC and what it offers/is capable of. Good luck! JColvin
  14. Hi @rappysaha, We're not fully certain about the differences between those two licenses as those of us here on the Forum are not Xilinx employees. I believe that the two licenses that you are referring to are the same license (I didn't see a "voucher" on the second license that you linked to though), so you would need to contact Xilinx in order to get a full and accurate description between specific licenses. Thank you, JColvin
  15. Hello, I have confirmed that the speed grade is indeed -7 and have updated the Resource Center to reflect this. The full FPGA part wasn't listed on the Resource Center (I didn't update it since I couldn't figure out an easy way to make it visually look good without having to break that one section into three different lines), but it is XC2C256-7TQ144C. The "-7" indicates the speed grade, and the "C" at the end indicates that it is a commercial grade part. I'll work on getting the other FPGA pages updated as I notice them. Thanks for helping bring this to light. JColvin
  16. Hello, I talked with our senior engineer for our microcontroller boards and they do not know anything about the SEGGER J-Link, so no, we as Digilent will not have any information on how to debug chipKIT boards with that particular debugger, at least in the foreseeable future. I was informed that JP3 and JP4 are JTAG/Trace ports for Imagination Technologies, but we don't really have any information beyond that. It looks like Imagination Technologies has a document from January of last year that talks about using JP3 on the WiFire though. I'm sorry I couldn't be of more help. Thanks, JColvin
  17. Hello, We're in the process of getting the Resource Center updated; I'm confirming if the -7 rating is accurate. Thanks, JColvin
  18. Hi Henry, I'm not the most familiar with the original Analog Discovery, but from my understanding the factory settings should be good to go. You can go through a calibration yourself though on the initial WaveForms page in case some offset has occurred in your hardware. An engineer more experienced with the Analog Discovery commonly checks this sub section of the Forum and will be able to provide more advice/correct what I've said if needbe. Thanks, JColvin
  19. Hello Muhammad Tufail, I know the Basys 2 is currently in a limited supply (at least as per our website), I would recommend contacting the Digilent sales team by emailing sales @ digilentinc .com for the most accurate information in terms of price and timing. I know we have a distributor based in Pakistan (http://www.rastek.pk/index.php), but it doesn't look like they carry the Basys 2. Thanks, JColvin
  20. Hello @Simon, I have moved your question to a more appropriate location on this Forum so that the appropriate applications engineer will be able to see your question sooner. Thanks, JColvin
  21. Hi @[email protected], Thank you for the feedback; this is a slightly different take than what the various higher ups were thinking the purpose of the chat channel would be (to get a faster turn around time for responses). While this is similar, it has a distinctively different flavor(?) than just getting a faster turnaround time, since I think that is an expectation associated with chat channels. The other concern that was brought up was the fact that we as Digilent would not be able to guarantee that we always have somebody available to talk to in the chat, even just during the weekdays, so there's hesitation of representing a channel that we couldn't give proper support to. I wasn't aware of the recording portions; that'll be a nice thing to show that the thought process of working through a problem will still be available. I'll definitely bring up the idea of that the chat better supports faster communication for a project so customers aren't waiting multiple weeks, but I think at this point Digilent will still stick with the Forum since there are also a number of examples where communication goes quickly between Forum posts; to be sure it's not as fast as the chat, but if it takes both parties a half day or full day to respond to the other (due to having other daily life tasks or whatever might be the case), I suspect it won't be considered as a dire need. That being said, I don't think there will be any complaint if a community chat channel was created (not that we could do anything to stop it anyway). I'll continue to look into this though and do some data collection here on the Forum to get some numbers since that'll be a valuable metric in the end. Again, thank you for the feedback, JColvin
  22. As a side note, I think it would be good if we created some sort of chat channel, if only because IPS (the company that provides this forum software) will retire their chat feature on May 1 of 2017 (as per their update here). More googling showed that other people had promoted IRC chats on the IPS forums with the CEO of IPS present on that thread (link), but evidently that didn't come to anything. As for the Digilent side of things, there isn't really anything we can do to prevent them from removing the current chat that exists. I'll look into the other options to see if they have some of the things that various higher ups at Digilent would want, but the biggest thing is that right now it is wished that the Digilent Forum is our primary means of support since it is a feasible way of helping customers while keeping a growing "database" of existing solutions that people can find on their own, since having extensive documentation on our Wiki on how to approach every problem isn't feasible (yay engineering!). That and I imagine Digilent would want their own branded version considering that we are a company and all, as opposed to a group of people, although as the Forum is a group of people we'll see how that can change things. I'll bring it up in a meeting later this week to get some initial thoughts on this. Thanks, JColvin
  23. JColvin

    NI ELVIS

    Hello usha_tiwari, Digilent does not sell the NI ELVIS, so we aren't able to offer proper support or guidance for using it. I would recommend posting your question in the National Instruments Forums instead. It looks like they have a forum specific to the ELVIS board here. I'm sorry I could not be of more help. Thanks, JColvin
  24. Hi Cristobal, I don't recall getting the Pmod AD5 working nicely; if I get the opportunity I'll try to take a look at it again, but I'm not certain when that will be. I think some of the changes I made were to the github code, but I don't recall at the moment. Thanks, JColvin
  25. Hello, This is just some friendly feedback on my part since I realize the software is still in beta, but I was taking a look at WFL again and noticed that I'm not seeing the labels for the Analyzer channel that Dharsan made reference to. Are those live or hopefully in a build that'll be pushed live soon? Also, (at least for me) it looks like the main viewing screen doesn't update with the waveform I've set from the waveform generator after hitting the "run" button. It doesn't update the screen until I hit the "stop" button while running (or by hitting the "single" button for just a lone acquisition). It also looks like that while running (presuming the waveforms are shown on the screen) I can have an analyzer line disappear from the screen, but not reappear. The waveforms (or at least the OSC1 and Waveform generator) also don't look like they disappear from the screen while the simulated OpenScope is set to run mode, even if I click their little power buttons. I'm not sure why the analyzers do that, but it seems like the others aren't updating maybe because once the run mode is activated it collects all of the current settings and sticks with it? It's a little weird since I'm not seeing the screen update until I hit the stop button (as I mentioned earlier). But I can make changes to the AWG while it's in run mode and see those changes when I hit stop, so that doesn't help my collect all of the current settings theory...hmmm. Mostly I figured I would mention this just in case a second pair of eyes was needed to help spot some of these things. Thanks, JColvin