JColvin

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Everything posted by JColvin

  1. Hi @T.Ono, If you download the latest version of WaveForms, available on the WaveForms Resource Center, https://reference.digilentinc.com/reference/software/waveforms/waveforms-3/start, you will be able reprogram your Analog Discovery (original) as described in this specific post here. The newer WaveForms (since it looks like your are using an older WaveForms based on your screenshot, also supports the original Analog Discovery. Let me know if you have any questions. Thank you, JColvin
  2. Hi @Derry, I apologize for the delay. To answer the quick question on Arty differences, the "Arty" and the "Arty A7-35T" are the same board. There was a branding change awhile back when Digilent decided to expand the product line beyond just "Arty". We have a blog post on it here. In terms of your actual question, I've sent you a PM with the application that you have seen mention of before, though it seems that you have tried the vast majority of what is readily available. As for clarification questions, when you power the board via the USB cable, what is the state of the p
  3. Hi @Tharun, There are a couple of links here on LabVIEW MakerHub that talk about using a servo with LabVIEW MakerHub LINX here and here. Thanks, JColvin
  4. Hi @rettile, I have sent you a PM about this. Thanks, JColvin
  5. Hi @Javier Romo, I have added an English translation to your post and moved it to a more appropriate section of the Forum. We have a demo for the Nexys 4 DDR that is available on it's Resource Center, https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start, that uses the seven segment displays available here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-gpio-demo/start. Let me know if you have any questions. Thanks, JColvin
  6. Hello @parvy, I am not aware of a sample project readily available for the Spartan 3A/3AN (Digilent made the FPGA, but Xilinx created all of the demos and reference material); Xilinx's user guide (link) indicates that there are design examples available, but the link does not seem to go anywhere. Chapter 5 of that user guide though does discuss using the on-board LCD at length, so that may be a good place to start. Thanks, JColvin
  7. Hi @Baker Steve, I believe attila contacted a different Digilent engineer to get their insight on the problem (malexander), who would be able to provide insight on the driver side of things. Thanks, JColvin
  8. Hi @Kopart, We're taking a look into this; I learned that the Nexys 4 DDR can come with either DDR2 memory (as you found), but I don't have the ISSI version on hand so I'm asking to see if another one of my co-workers in a different office can test this out. Thank you, JColvin
  9. Hi @kursatgol, Our engineer was able to get the XUP cable recognized and working on a Centos 7 64-bit VM with Vivado 2018.1 without much issue. The main thing that they did (detailed in the Installing Cable Drivers section of Xilinx UG973) and went to their install_install drivers directory (../data/xicom/cable_drivers/lin64/install_script/install_drivers) and executed the ./install_drivers script as sudo. They were then able to run Vivado and use the hardware manager as normal to connect to the cable and have Vivado 2018.1 successfully auto-connect to the XUP USB JTAG cable and the downs
  10. Hi @BobA, I don't necessarily know all the answers to your questions, but I'll answer what I can. - If they're on the PC, why are there only 10 buffers? (Ah ... I just discovered a settings dialog that lets me increase the number of buffers. Is that documented anywhere?) -- yes, this is within the WaveForms software itself. Inside the GUI, click on the Help tab at the top, then Browse. The WaveForms documentation stored on your local machine from when WaveForms was initially installed will be brought up and you can find the details about the Buffers in the gear menu in the "Logic -&g
  11. Hi @hjain, I apologize for the delay. Our design engineer was to get the XUP USB JTAG cable to work in Vivado on Windows 10; the install script that Xilinx runs as part of cable driver installation does not work correctly. What they had to do was the following: Let me know if you have any other questions. Thanks, JColvin
  12. Hi @kursatgol, I apologize for the delay. Our design engineer was able to get it working in Windows 10 (the install script as part of the Xilinx installation process for the cable drivers is not working correctly), and plans on trying to get the cable drivers working in a Linux distro. I'll let you know what I find out. Thank you, JColvin
  13. Hi @Imjustatech, If you want to do some command line utilization with Adept 2, what you will want to use is the Adept Utilities which is available for download on the right hand side of the Adept 2 resource center. My understanding is that the part of the Adept Utilities that you will want to use is the djtgcfg. Let me know if you have any other questions about this. Thanks, JColvin
  14. Hi @Maher, None of us here at Digilent have used an SOM to program an FPGA through a JTAG-SMT2. Depending on what FPGA you are using, you may be able to use Digilent's Adept 2 software to program the FPGA, though Adept 2 does not have built-in support for every FPGA, such as the Xilinx Ultrascale and Ultrascale+ parts. I would recommend contacting the manufacturer to see if they have a recommendation or an existing setup that you could modify to target the board of your choice. Thank you, JColvin
  15. Hi @Mazen, Unfortunately we do not have any formal tutorial on using the ISERDES and OSERES IP blocks. There are a couple of threads discussing the SERDES capabilities of Xilinx boards here, here, and here. Otherwise, I would recommend posting on the Xilinx forums and potentially taking a look at this Xilinx thread as well. Thanks, JColvin
  16. Hi @mma, A mechanical file with dimensions for the BNC adapter is available on it's Resource Center here on the right hand side under documentation. I don't think it has any vertical dimensions on it though. I don't think we have any dimensions readily available for the original Analog Discovery. I can try to find some dimensions for it though, but it would be measurements that I took with a pair of calipers rather than formal measurements; you are looking for the dimensions on the PCB itself rather than the existing casing? Thanks, JColvin
  17. Hi @bshelburne, I moved your question to a more appropriate section for you. As for the error that you are getting, it looks like the error is suggesting that the switches and LEDs that you named/instantiated in your module do not match the names that are specified in the .xdc file. What you can do is change the local project copy of the .xdc file within Vivado to match the names in your project. An example of this is available on our on steps 16 and 17 of this tutorial on our Wiki here: https://reference.digilentinc.com/learn/software/tutorials/verilog-project-2/start. Let us k
  18. Hi @Imjustatech, I apologize for the delay. Since the chip your customer is using seems to be a Xilinx automotive chip, those particular map files are not loaded into Adept, so Adept is not able to recognize it and properly program it on it's own unfortunately. You would either need ISE installed or your own custom application in order to program that chip, however from what I recall, the ISE that Xilinx released for Windows 10 only supports Spartan 6 devices, so I do not think it will readily work in that case. Thank you, JColvin
  19. Hi @ArKay99, I ran the project as is from the downloaded file as on Vivado 2016.4 and it generated with no errors and everything looks as it should. I was also able to have it generate a bitstream successfully as well and launch on SDK as well. What commands did you use to create the project? In the readme there is a small typo when running the create_project script. I don't know if you corrected it already but the correct formatting is as follows (modified for the path of where I stored my project when I ran it for the Zybo Z7-20): cd C:/Users/jcolvin/Documents/VivadoPrj/zybo_z7
  20. Hi @syu, I was checking at the same time as @jpeyron, but it looks like the resolution of the Pmod ISNS20 current sensing chip (link to manufacturers website for the ACS722) is 66 mV/A. So, if you were wanting to measure with a 0.1 mA resolution, that would equate to about 6.6 uV detection capabilities, which between the sensitive error of the current sensor and the resolution of the attached ADC (0.732 mV per LSB), the Pmod ISNS20 will not meet your needed capabilities. Thanks, JColvin
  21. Hi @rahulgujaran, Which Zynq hardware are you using? A Zybo, Zybo Z7-10 or Zybo Z7-20, Zedboard, or something different? Thanks, JColvin
  22. Hi @jhauser-us, I am also concerned to hear this since I don't get to hear very often about that side of the business. Which particular Arty were you and your friend using (the original Arty or the Arty Z7-20) and do you happen to remember what revisions the boards were so that I can make sure from my end that the appropriate engineers are looking into this with the information they need? Additionally, is there anything unique about your power supply or is it a fairly standard 12V-3A supply with a center positive plug? What sort of designs were you working with, i.e. smaller designs
  23. Hi @Flux, Thank you for taking the time to share your project! Thanks, JColvin
  24. Hi @ArKay99, I'm not in the office to check this for certain, but offhand I would guess that the out of the box demo you downloaded from the Zybo Z7 Resource Center does not include all of the necessary materials in the .zip. I'll double check this and make sure it gets updated tomorrow. What you can try in the meantime is the HDMI demo project that is in the example projects above the additional resources section for another demo that doesn't require some additional hardware that you might not have ready access to. Thanks, JColvin
  25. Hi @nick hamilton, I have moved your question to a section of the Forum where the engineer much more familiar with the Analog Discovery 2 and the WaveForms software will be able to see and respond to your question. Thanks, JColvin