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Everything posted by JColvin

  1. JColvin

    Editing the XDC file

    Hi @Newport_j, Whatever naming convention for the XDC file that you downloaded and saved to your computer is correct. The biggest thing that you will need to make sure of is that the file name (whatever it might be) has an ending of .xdc The master XDC file does not have to be changed in any way, it can remain as is, serving it's purpose as the master copy. The file that you load into Vivado in Step 6 of the Getting Started Guide will be changed though. You will want to uncomment (by removing the # symbol) lines 8, 9, and 27, as shown in the image associated with Step 6.5.
  2. Hello @mitchpitch, My comment was incorrect; I'll change it. The part always has an adc read of 16 bits from -5 to +5 volts. The only difference is if you choose the 16 bits to be represented as 0 to 65535 or from -32768 to 32767. The DACs also output from -5V to +5V. Let me know if you have any questions about this. Thanks, JColvin
  3. JColvin

    Editing the XDC file

    Hi @Newport_j, You can open up the XDC in Notepad (if you are using Windows) or in a different text editor like notepad++. But yes, that image does not look correct. What I would to do (and personally do for myself) get the XDC file edited and saved is: - Go to the Zybo-Z7 XDC on Digilent's github (here) and copy and paste all of the text into some sort of text editor. - Save the master XDC file (making sure you save it with a .xdc extension, even if your program doesn't recognize it and you have to type it in manually) to your computer where you can find it later - whe
  4. Hi @jfdo, The URL doesn't change when we move a thread so it can always be readily found with the existing link, but the section of the Forum did change to Scopes and Instruments where the creator of the WaveForms software commonly looks. Thanks, JColvin
  5. Hi @ricardo, I would recommend posting on the NetFPGA Forums here. The NetFPGA community will be able to provide much more direct and helpful advice than those of us here on the Digilent Forum can provide for the NetFPGA SUME. Thank you, JColvin
  6. JColvin


    Hi @UOB, I sincerely wish that we (Digilent) could help you. The unfortunate reality is that we have no way to adjust or influence how the Xilinx software is set up or any of the policies associated with it, nor do we have an alternate solution that we can offer to you. I'm sorry I could not be of more help. Thank you, JColvin
  7. Hi @Chetan,. I have moved your question to a more appropriate section on the Forum where Attila commonly checks. Additionally Attila is in a different timezone than jpeyron and I, so it may until tomorrow until they are able to respond. Thank you, JColvin
  8. JColvin


    Hi @UOB, I do not know this for certain, but your issue may be related to this Answer Record from Xilinx. Unfortunately, as Digilent does not make the ISE or Vivado software we will not be able to assist you in this, though Xilinx does provide an email in that answer you can contact about this rather just posting on their Forums. I'm sorry I could not be of more help. Thank you, JColvin
  9. JColvin


    Hi @UOB, Digilent does not and has not provided any licensing files for the Xilinx ISE or EDK software, so unfortunately we will not be able to help you in that regard. When you say "we cannot generate the bit file for the target device", are you attempting to program the Basys 3 with ISE 9.2? My understanding is that none of the ISE software, whether 9.2i or the last 14.7 version released in 2013, are able to target xc7A35t FPGA present on the Basys 3; only Xilinx's Vivado software is able to target and generate a bitstream for that particular FPGA chip. I believe ISE 9.2i (I person
  10. Hi @Starless, That will be a question for our Sales team, whom you can contact by emailing sales @ digilentinc . com. Those of us here on the Forum unfortunately do not if that is possible or not. I'm sorry I could not be of more help. Thank you, JColvin
  11. Hello @subasheee, I ran the same project on Vivado 2016.4 for the Nexys Video XADC and all the values were being measured as expected. There are a couple of pictures here and here of my setup, with the blue rails on the side as my ground wires. I'm not certain how yours is set up but one thing that I did notice is that I needed to have all of the positive input of the pins connected to something rather than just floating, otherwise they would float around 200 mV or so and if left floating would fluctuate with inputs provided to the other pins. In particular pin 3 (the A8) would very
  12. From the album: Forum photos

    Physical connection of the XADC rig to the Nexys Video using a Pmod TPH2 (a passthrough Pmod) and a Pmod DIP (to connect the 2x6 connector to straddle a breadboard).
  13. From the album: Forum photos

    Orange wires on the left of the Pmod are grounded pins. Wires right of the Pmod are the analog inputs (or a ground wire) for the positive inputs to the XADC on the Nexys Video
  14. Hi @Newport_j, Yes, that is the correct file for the Zybo-Z7-20. Let us know if you have any other questions. Thanks, JColvin
  15. Hi @BeatIdo, The restart condition is part of the I2C protocol methods; it's also known as a repeated started condition. It is done the same way as a start condition by pulling the SDA line low while the SCL line is high. Let me know if you have any questions about this. Thanks, JColvin
  16. Hi @ArcaGraphy, As some further information, the OLED display won't immediately display the Digilent logo unless you program it to do so and we didn't create a formal demo doing so. I did create a custom image that loads the logo onto the screen back in 2014 that was badly written for a microcontroller though. Here is the set of characters that I used to create the image: Thanks, JColvin
  17. JColvin

    Arty S7 step file

    Hi @icedefender, The Arty S7 CAD model is now available on it's Resource Center at the bottom of the page under Additional Resources. Thanks, JColvin
  18. JColvin


    Hi @Newport_j, I have not gone through Xilinx's tutorial, but I imagine the demo would be functional with the Zybo-Z7-20, after some appropriate changes where made (since it is a different FPGA chip). Alternatively, it looks like Xilinx has some Workshop material available for HLS on Zynq boards on this page, with what appears to be some material from previous years on the right hand side of the page: https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-high-level-synthesis-flow-zynq.html. Thanks, JColvin
  19. JColvin

    Looking at Arty S7...

    Hi @Hal, My understanding is that the Vivado HLS (what gives C and C++ capabilities) is now included with the WebPACK Edition of Vivado. I'm not certain if anything further becomes available with the paid versions of Vivado or not, (Xilinx would be the authority on this), but their documentation on HLS does not seem to indicate this. Thanks, JColvin
  20. Hi @subasheee, I have moved your question to a more appropriate section of the Forum. When you are measuring the XADC, are you putting ground on the negative input pins (the ones below AD1, AD0, AD8, and AD9)? Thanks, JColvin
  21. HI @dna35, It looks like your question was answered on this thread here. Let us know if you have any other questions. Thank you, JColvin
  22. JColvin

    Basys 3 D1-8 components

    Hello @zener, Here is the datasheet for those diodes: https://www.onsemi.com/pub/Collateral/NSQA6V8AW5T2-D.PDF. Thanks, JColvin
  23. JColvin

    Arty S7 step file

    Hi @icedefender, I will have to request for a model of the Arty-S7, but there is a mechanical pdf file for the Pmod Clip on its Resource Center. Thank you, JColvin