JColvin

Hi @sminded, Which Digilent board do you have so we can provide some accurate feedback? Thanks, JColvin

Welcome!

Minor follow up, I looked at the UG475 that zygot referenced, and best that I can tell from Chapter 6 Package Marking, the speed grade used to be its own individual line on the 4th row down, just below the lot code (detailed slightly more in Table 6-1). But based on figure 6-4 for the Artix FPGA (and the equivalent figures for the Kintex and Virtex FPGAs), this is the "Legacy Artix-7 Device Package Marking". I'm not certain when this change occurred, but it was a number of years ago as I have Basys 3 Rev C's (Rev D came out in 2021) both with the speed grade marking and without it. Thanks, JColvin

Hi @dsdsd, From what I can recall, no Digilent device uses a FT2232HL. Digilent's programming solution is made exclusively for Digilent boards and so will not be able to restore a different development board from a different manufacturer. In terms of just generically erasing material, FTDI's FT_PROG application may be able to help you, though it is also likely a common reason for the many users that ended up posting on this thread to begin with. Thanks, JColvin

Hi @Taksun, Digilent typically uses the FT2232HQ device (such as is mentioned in the Arty A7 Reference Manual here: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual#usb-uart_bridge_serial_port). I have not done any research into the 56-pin variant, nor I am I sure by what you mean that it does not work as a Digilent programmer, as that seems to imply you have already attempted to configure the device, though I do not know how you would have done so. Regardless, I would not be surprised that with the reduction of pins comes a difference in pin layout as well as register configuration, so I would imagine that Digilent's programming solution as it currently exists would be incompatible with the FT2232H-56Q. Thanks, JColvin

Hi @Frank.L, I have sent you a PM. Thanks, JColvin

Hello, I had forgotten to update this thread with the reply I received a week later: Thanks, JColvin

Hi @jfrenzel, I believe this is because you have the Mode dropdown set to "Standard" rather than "3-wire". With the Standard option, it looks like WaveForms still tries to read what is being transmitted on the DQ1 line; as there is no DQ1 line set, this ends up defaulting to all zeros. Let me know if this does not resolve what you are experiencing. Thanks, JColvin

Hello, I have moved your question to a more appropriate section of the Forum where an engineer more experienced with Linux mode on the ADP3450 can provide a more accurate answer than myself. Thanks, JColvin

Hi @john-con, I can confirm that the Arty A7 and Basys 3 both use speed grade 1 components. I'm not certain off hand where you would readily determine this off of the chip labeling itself, but you can see the critical "-1" portion of the FPGA name in the right hand side of their respective Resource Centers, https://digilent.com/reference/programmable-logic/arty-a7/start and https://digilent.com/reference/programmable-logic/basys-3/start, of the "FPGA Part #" row. As far as I know, zygot is correct that only Digilent's Genesys 2 has a speed grade 2 part. Let me know if you have any questions. Thanks, JColvin

Hi @arang, Not in the Protocol tool specifically, but you can adjust the drive strength, slew, and pull values of the IO pins either through the Supplies instrument or through the Settings -> Options -> DIOs tab. I'm not certain what you mean by duty cycle specifically, but you can change both the System Clock frequency that the Digital Discovery uses at large though those same settings, or you can change the frequency of whatever protocol you are using through the (user typeable) dropdown within the Protocol tab of interest as well. Let me know if you have any questions. Thanks, JColvin

Hi @idegani, As far as I am aware, it's not possible to have a particular configuration loaded on power up as the on-board FPGA will not maintain it's configuration once power is disconnected. The workaround that might work for you would be to use the "Continue" option for what the device does when WaveForms is closed within the WaveForms Device Manager. As long as the device is still receiving power (either over USB or via an external supply), the device will continue to operate in whatever configuration/state it was last set in. I routinely use this when I'm testing other devices but want to limit the total USB activity and ports I am using. There are a couple of other threads that discuss this option here: Let me know if you have any questions. Thanks, JColvin

Adding on to what zygot mentioned, you'll find that many mobile phones will also randomize their MAC address when connecting to a WiFi network by default (Android has some information on it here: https://source.android.com/docs/core/connect/wifi-mac-randomization-behavior), because (in my limited understanding of network operation at large) this would be a localized address within that subnet, so the odds of matching somebody elses MAC address within that same small amount of devices is quite small. Regardless, localized or unique MAC, you'll have a bad time if there is a match as the different communication frames will end up at the wrong device, so that neither device works properly. But that is about as far as my knowledge goes on this particular topic.

Hi @CG73, The Analog Discovery 3 does not come with any sort of calibration certificate/report. However, the individual calibration values are stored within the device and can be viewed within the WaveForms Device Manager by clicking the "Calibrate" button. From there you also have the option to individually calibrate different instruments, or to reload the factory calibration as needed for your device. Digilent does not have any specific recommended calibration schedule. There is some additional information in the WaveForms Help tab here: Personally, I recalibrate my device before I start doing a larger project with it. Let me know if you have any questions. Thanks, JColvin

Hi @Jerin James, The Eclypse Z7 board does need to have the 12 V external power attached and board powered on before the corresponding FTDI chip and the downstream Zynq device to be detected by the Vivado Hardware Manager. Presuming you have it powered, is the Digilent Adept software, https://digilent.com/reference/software/adept/start, able to see the Eclypse Z7? (I'm asking specifically for Adept since the Vivado software suite uses the drivers that come from Adept, so this is the effective equivalent of installing the drivers from source). If Adept does not see the board either, what do you see in the Windows Device Manager / kernel output with dmesg (depending on the OS)? An example of what you should be seeing in Windows is in this post, and a similar one for Linux is here. Let me know what you find out. Thanks, JColvin

Hi @Hiroaki, This is detailed some in the troubleshooting guide, but if you know that you erased the FTDI chip, you may be able to recover it from the WaveForms Device Manager. Go to the More dropdown and select ProgAD1,2,3,ADS,DD in the menu option and then follow the directions. I'm not certain what version of WaveForms you might be using since you are using the original Analog Discovery, but the latest version is freely available and supports it here: Let me know how it goes. Thanks, JColvin

Hello, Digilent sells a compatible cable on our store here, https://digilent.com/shop/usb-a-to-micro-b-cable/, but in theory any micro-B cables that support USB 2.0 speeds should work fine. The two cables that I use daily at my desk don't have any branding marked on them. The benefit of buying/paying for shipping for the USB cable from Digilent would be that if you still experience disconnect issues is that it would quickly narrow down the possible points of failure. I don't know when/where you purchased the Cora Z7 (I don't have access to such data), but it's my understanding that when purchasing an FPGA from Digilent, you can optionally choose to add the appropriate USB cable for free to the purchase (the button for that is directly below the price listing; example on the Basys 3 page here: https://digilent.com/shop/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/). This looks somewhat easy to miss though, so I'll submit that as feedback to the web team. Thanks, JColvin

Hi @Lou Williams, Your code seems to be working fine for me with no changes when I supply a rising edge signal to DIO 0, or at least a pattern starts dutifully running continuously on DIO 6 and 7. What about it is not working? Is the pattern just not starting from the external rising edge or? Thanks, JColvin

Hi @gaetan, Unfortunately, Digilent does not have Mean Time Between Failures for any of our products, Cmod A7 or otherwise. Thanks, JColvin

Good choice; only one of us is the WaveForms developer and its not me.

Hello, So, the 1.5 A total for the 5 V rail that I mentioned is listed in Table 7.1.1 in the USB104 A7 Reference Manual (https://digilent.com/reference/programmable-logic/usb104a7/reference-manual#zmod_port), is not a SYZYGY Specification. It is a design choice made by Digilent. You can see that the SYZYGY 5 V rail is limited to 1.5 A on the first page of the USB107 A7 schematic in the power tree diagram. I am not certain where you are getting from the Power Rail Specifications Table 1.2.1 that the 5 V rail can supply 3 amps. The line entry I presume you are looking at is for the 3.3 V rail, which is derived from the 5 V rail, as noted by the "upstream net name" in the second column. Regardless, you cannot supply more than 2 amps to the 5 V rail as per Table 4.1 in the SYZYGY (not Digilent) Specifications: http://syzygyfpga.io/wp-content/uploads/2023/09/Syzygy-Specification-V1p1p1.pdf. The reason why Digilent provides a 5 V 6 Amp power supply (30 Watts total) is to meet the power budget outlined in Table 1.2.1 as each rail (the Net Name column) is derived from the VCC5V0 net. Let me know if you have any questions. Thanks, JColvin

Hi @sand, You'll be wanting FDwfDigitalIOOutputEnableSet and FDwfDigitalIOOutputSet which are defined in the Digital IO section (section 8) of the WaveForms SDK Reference Manual. DigitalIO.py in the samples folder uses these two functions, enabling DIO 0 to 7 as outputs and then setting IO pins 2 and 5 as logic high. Let me know if you have any questions (or if I misunderstood what you are wanting to do). Thanks, JColvin

Hi @DavidD, There are a couple of likely culprits causing this issue. One is a USB cable of insufficient quality or bad connection (bad connection also could happen if you are routing the cable though an already busy USB hub). The second could be inconsistent power, potentially from the USB cable (also an issue with a busy). What I would personally be attempting to resolve this is to try both a different USB cable and USB port (I have had both fail on me before). Let me know what you find out. Thanks, JColvin

Welcome to the Forum!

Hello, Your question is valid. I asked one of the hardware engineers to see if there was some insight that I was missing, but they let me know that the 6-pin external JTAG header is purely as a backup option. You can still load bitstreams/.bins from the Vivado Hardware Manager as well as applications from Vitis (I loaded an HDMI example onto a Zybo-Z7 via a JTAG HS2 just now) but you still don't have direct access to UART nor the PS_POR_B pin for processor resets. Let me know if you have any questions. Thanks, JColvin