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Everything posted by JColvin

  1. Hi @Raghunathan, Could you attach a picture of your settings? I was unable to replicate the situation regarding the peak to peak voltage (my screenshot is using 50 Hz, but 60 Hz did the same as well). With regards to the square wave appearing curved, I was only able to see this when I zoomed in so that the time base was at 2 uS/division or less but at that point you are just viewing the output settling time of the requested change which should be about 580 nS as noted on slide 91 on the detailed Microchip Masters Presentation. Thanks, JColvin
  2. Hi @perdue, My understanding is that the Adept tools are not configured to detect the on-board Ultrascale+ board as it is not built into the Adept system. You would need to use the Xilinx hardware manager to program and otherwise interact with the VCU118. Thank you, JColvin
  3. Hi @dumbguy, None of these signals in your workspace seem to indicate a SPI protocol. DIN0 and DIN3 seem to be inverse polarity of each other, DIN1 and DIN2 seem to pulse about 8 uSec apart from each other with 16 pulses between the synchronous pulses between DIN0 and DIN3. It also generally (with exception to the 7th pulse on DIO8 and the entirety of DIO11) seems to follow that on every falling edge causes a change on a higher order clock; i.e. every falling edge on DIO8 corresponds with a change on DIO9, and every falling edge on DIO9 corresponds with a change on DIO10. The rapid pulses on DIN1 and DIN2 occur after transitions on DIO8-DIO11 so I do not think they are clocking those longer pulses. I am not certain what protocol represented in general might be though DIN8-DIN10 (aside from the odd 7th pulse on DIO8) is reminiscent of a decimal counter. Either way, I agree with you that there is not any line indicative of being MOSI or MISO or any data line. I would probably ground the black wire to help prevent any spurious issues, though I am not seeing any evidence of problems of cross talk in your attached workspace. Thanks, JColvin
  4. Hi @Glenn Kasten, I don't know why the solutions are provided in a .rar format; as far as I am aware, everything else on the Digilent website (Wiki site and Github included) that is in some sort of packaged format uses the .zip format. I suspect the solutions are done this way because that is how the solutions were provided to us, but I will ask about getting it changed to a more user accessible version. Thank you for pointing this out. Thanks, JColvin
  5. Hi @zliu, I'm not certain what the issue might be. What I will recommend would be to start an RMA. I have sent you a PM with some details that our sales team would need. Thanks, JColvin
  6. Hi @PortAxe, Digilent doesn't have any specific material for the Pmod OLED for the Raspberry Pi. There is a Pmod HAT adapter available that does have some Pmod software support from DesignSpark and RS Components, which does have a library example for the Pmod OLEDrgb. The main SPI pins (including the two chip select pins) are present on GPIO 7, 8, 9, 10, and 11 on the 40 pin Raspberry Pi header. Thanks, JColvin
  7. Hi @alediben, I heard back from the other engineer. They said that since you are considering the SMT2 rather than the SMT3 VBUS does not need to be connected to the module. However, they mentioned that the USB 2.0 specification has an inrush current requirement and as a result, an associated minimum bus capactiance for a usb device and recommended placing a 1.0uF or 2.2uF (10 volt or higher rated) ceramic capacitor between VBUS and GND near the connector, even if you don't intend to draw power. Thanks, JColvin
  8. Hi @zliu, Digilent does not have a tech support phone line, primary because many of the topics that need troubleshooting are ill-suited for an audio based discussion. Since you have not explicitly said so, have you tried a different cable? My understanding is that even if the EEPROM to go with the FTDI solution on the Digilent boards is corrupted in some way, Windows will still recognize that the boards are connected to the computer, albeit as an unknown device. Since nothing is being detected in the Windows device manager (I can't tell if there is anything in your device manager that has an error flag next to it). Thanks, JColvin
  9. Hi @zliu, Have you gotten to try other USB cables? What version of the FTDI driver do you have installed; the latest version (2.12.28) is available on the FTDI website here: https://www.ftdichip.com/Drivers/D2XX.htm. Thanks, JColvin
  10. Hi @wchao_iris, You will likely need a higher voltage for the Pmod I2S2; the Analog to Digital converter chip (CS5343) has a minimum recommended operating voltage of 3.1V, so it will likely not operate correctly when you are trying to debug/listen to incoming analog signals. Is the SCLK clock you listed supposed to be 6.144 MHz? Since I suspect it is not over 6 GHz. Thanks, JColvin
  11. Hi @alediben, I have asked another engineer about this. Thanks, JColvin
  12. Hi @zliu, If you have tried different boards, then I agree that it is not board specific. Could you attach a picture of how you have the board setup while plugged in in case I can spot something weird? And has the board ever worked for you? What do you see in the Windows Device Manager? Normally the Arty board (both S7 and A7) will show up as a "USB Serial Converter" (maybe with an A or B at the end of it) under the Universal Serial Bus Controllers section. Additionally, do the boards themselves power on? One thing to try if you haven't already would be to try a different USB cable (since some USB cables that come with phones are only designed for charging rather than also data) and potentially a different USB port. Thanks, JColvin
  13. JColvin


    Hi @Sean Kelly, I don't think there is anything like that directly available for the Zynq, or at least I am not able to find anything like EMCCLK in the Zynq Packaging and Pinout Guide (UG865) whereas it is available in UG475 for the non-Zynq 7-series boards. Thanks, JColvin
  14. Hi @Leo_W, I have moved your question to a more appropriate section of the Forum where the engineer most familiar with the Analog Discovery Studio will be able to see and respond to your question. Thanks, JColvin
  15. Hi @HKPhysicist, I apologize for the delay; I thought I had already responded. 1. As it currently stands, there are not any digital protocols that are supported 2. It currently only detects rising and falling edges of a digital signal 3. I am not aware of any sigrok support for the OpenScope MZ Thank you, JColvin
  16. Hi @zliu, I apologize for the long delay. The cable drivers should be part of the Vivado installation, though they are an optional installation so there is a chance that they are not installed. You can reinstall the cable drivers as per this Xilinx Answer Record: https://www.xilinx.com/support/answers/59128.html. Let me know if you have any questions about this. Thanks, JColvin
  17. Hi @macellan, Could you attach a picture of your block design? The description of your steps sound correct (and the running connection automation can add some more items depending on when individual pieces of the block diagram was added and when connection automation was run). As for when different pieces were added to the block diagram, it can make a difference, but really only during the Connection Automation and Block Automation when you tell Vivado what sort of connections you would like it to make. Otherwise, the 2018.2 guide should work fine for 2019.1. Thanks, JColvin
  18. Hi @dumbguy, One thing that you can do is add multiple SPI bus analyzers each with their own individual chip select associated with it. The MOSI, MISO, and CLK can be all be shared between the individual bus channels (much like SPI in actual hardware) so you can more easily differentiate which data is associated with which sensor based on the status of the CS line. I have attached a picture of how this might look in WaveForms (I don't have a Digital Discovery with me at home so my screenshot is from demo mode). I wouldn't be surprised if the sensors were continually being read, especially if they were set up so that they (the sensors) automatically collecting data and then sending the data as soon it was inquired, then between multiple sensors, it could be very easily set up to read data from one sensor (then letting it collect more data) as data is read from the next sensor, then the next sensor, effectively in a round-robin fashion with no downtime. Thanks, JColvin
  19. Hi @Sean Kelly, I personally do not know this information, but I have asked our layout engineer about this. Thanks, JColvin
  20. Hi @tcal-x, All of the boards should have the out-of-box demo working. One thing to check would be is if JP1 jumper is set with the shorting block to enabled the SPI flash mode which is where the out-of-box demo would be stored. Otherwise, a known working bitstream would be the best way to test; one such project is available on our GitHub (and I believe it may be the out of box demo, I don't recall for certain) here: https://github.com/Digilent/Arty-A7-35-GPIO. Let me know if you have any questions about this. Thanks, JColvin
  21. Hi @dumbguy, SPI was designed such that there are 3 primary lines that are shared between all connected devices; MOSI, MISO, and CLK. As you noted, there can be multiple chip selects that can individually signal different connected devices when the master device is communicating with them specifically. In terms of the number of bits that are transmitted at a time, each device will transfer a number of bytes to properly encompass the corresponding number of bits. My understanding is that any extra data signals are outside of the SPI protocol and are specific to the chip. What device are you attempting to monitor? Thanks, JColvin
  22. Hi @Shivani, I would recommend taking a look at these threads on our forum for some additional details on your endeavor: Thanks, JColvin
  23. JColvin

    Arty S7-50

    Hi @Saher, I have sent you a PM as well, but Digilent does not control the Export Controls that Xilinx is subject to with the Vivado software. If Xilinx is not able to further assist you with this, then my recommendation would be to return the board to whomever you purchased it from (e.g Digilent or a distributor). Thanks, JColvin
  24. Hi @nigelm, We are in the process of updating our material for Vivado 2020.1; I believe the materials for the Pmod IP library has been updated and is available here: https://github.com/Digilent/vivado-library/tree/feature/pmod_update. In terms of the specifically updating examples, a number of projects may be able to updated on their own by opening the project in 2020.1 and then running through the Reports->Report IP Status within Vivado and then upgrading those IPs (via the button of the same name at the bottom of the Vivado). If the project includes a Digilent made IP, we may need to update it ourselves if it not readily compatible with the latest version of Vivado. Thanks, JColvin