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Everything posted by JColvin

  1. Hi @Lukas G, Could you let us know what the two serial numbers for the two JTAG HS3's that are listed in the Vivado Hardware Manager? We want to make sure that the two boards do not happen to have the same serial number. Thanks, JColvin
  2. Hi @greengun, No, the transceiver pins on the Arty A7 FPGA (a XC7A35TICSG324-1L FPGA) are no broken out. As per Xilinx UG475 (page 41), the HR I/O bank 16 is only partially bonded out, but as per the Arty A7 schematic, the HR I/O pins on bank 16 are not used. Thanks, JColvin
  3. Hi @Lukas G, I have reached out to another engineer for their thoughts on this, but I wanted to confirm that you have the latest FTDI driver (2.12.28 in this case). I know you said randomly, so I presume that you have not observed that Vivado Lab Edition is taking control/enumerating the JTAG HS3 while you have Digilent Adept "attached" to the JTAG HS3 or any other boards or software being plugged in or started that would want to talk to the FTDI chip? Have tried using a different USB cable or USB port on the desktop to help rule out that particular hardware failure? Thanks, JColvin
  4. Hi @Victor, The project will still work despite the message stating the design failed to meet the timing requirements. I re-generated the bitstream for your project (leaving it otherwise as is) and successfully ran it and displayed the demo image on the monitor. Thanks, JColvin
  5. JColvin

    Software to Get started

    Hello, The board files (https://github.com/Digilent/vivado-boards) have been updated to fix the typos. Please let us know if you happen to see any other issues. Thanks, JColvin
  6. JColvin

    Software to Get started

    Hi @Robert R, The Arty S7-50 only has a Rev B while the Arty S7-25 has a Rev E, so the revisions are correct. I will request that the label for the SPI connector is correct to J7; I confirmed within the board files that the physical FPGA pins are defined correctly, but the label is wrong for this particular SPI connector. Thank you for pointing this out. If you still need it; we have a guide that helps you set up a Microblaze based design available on our wiki here: https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Thanks, JColvin
  7. JColvin

    Microblaze DDR RAM

    Hi @ozden.erdinc, I apologize for the delay. I would recommend taking a look at these threads (link, link, link)that discuss using the DDR with Microblaze (or at least have links to it) for the Arty A7 board. Thanks, JColvin
  8. Hi @sab, There are some FPGA gurus that will likely have some more specific advice with regards to the FIR filter utilization itself, though I suspect the amount of resources it "should" use are largely dependent on how it was designed and what you need it to accomplish. This will also give better insight as to how many LUTs your design should be using, though considering that your design is only using about 1% of the available resources on the Kintex chip, it's not what I would call a heavy design at least for this particular FPGA chip. As for the resource names, FF is for Flip-Flops, DSP is Digital Signal Processing (slice), IO is the amount of input/output pins on the FPGA, and BUFG are global clock buffers. Thanks, JColvin
  9. Hi @tauquir_iqbal, Are you using the Analog Discovery 2 like in your previous posts? Or more specifically, is this question a direct continuation to the one you had in this thread? Thanks, JColvin
  10. Hi @300cpilot, I would recommend loading the Nexys Video GPIO demo to confirm the UART port (presuming that is the one that was replaced) is transmitting serial traffic. Thanks, JColvin
  11. Hi @bradlynch, You can find the volatility information specifically for the JTAG HS3 in this post here: Thanks, JColvin
  12. Hi @Ranjani@V, Unfortunately, those of us here on the Digilent forum do not have much experience with EDK or the Virtex 5 boards. I would recommend asking on the Xilinx forums for more accurate advice regarding your situation. Thanks, JColvin
  13. That's alright; I'm glad you were able to get it working!
  14. Hi @yildizberat, I ran the project that I linked to earlier in Vivado 2019.1 without any issues. When I first opened it, Vivado informed me via a popup that it was an older project so I allowed it to automatically upgrade the project. It then wanted to upgrade one of it's IPs (which you can view the list of which IPs that it wants to upgrade via the Reports tab -> Report IP Status. I had Vivado upgrade all of those IPs (leaving the core disabled, presuming that is the default option when asked to upgrade the IP). Once the IPs were upgraded, I regenerated the bitstream and then programmed the Zybo Z7-10 with the bitstream and the 1920x1080p monitor I have connected is successfully displaying the premade pattern. I did not need to reconfigure or open the clocking wizard IP. To confirm, do you have the Digilent board files installed (tutorial available here)? Thanks, JColvin
  15. Hi @yildizberat, What version of Vivado are you using and what monitor resolution do you have? I used the 2018.2 release available here: https://github.com/Digilent/Zybo-Z7-10-Pmod-VGA/releases successfully. I did end up regenerating the bitstream to get it to work successfully though. Thanks, JColvin
  16. Hi @Takashi "The Yaka mein", We have a 3D model of the Pmod RS485 available in it's Resource Center on the right hand side under Documentation. Let me know if you have any questions. Thanks, JColvin
  17. Hi @Ashish Kashinath, I would recommend asking the NetFPGA Group directly via NetFPGA mailing list (link if you are not already signed up) which have more experience specifically running the acceptance tests, if only for the reason that they are the people who developed and maintain the acceptance tests. Thank you, JColvin
  18. Hi @sjalloq, If you are using Vivado, is there are a particular reason you are wanting to use an mcs file rather than creating a .bin and loading it onto the flash through the Hardware Vivado Manager? We have a tutorial that describes how to do this for the Nexys 4 DDR (now rebranded to Nexys A7) here. I found an old Xilinx thread that discusses creating the mcs file through Vivado, but it seems that in the end you still need ISE iMPACT to then be able to load that file onto the flash memory. Let me know if you have any questions about this. Thanks, JColvin
  19. Hi @Tinus, I have sent you a PM about this. Thanks, JColvin
  20. Hi @Lorenzo, Unfortunately, you will not be able to avoid pressing the PROG button. The reason you need to press PROG is because the bootloader will only load upon power-up/reset. You will also need to have the Let me know if you have any questions about this. Thanks, JColvin
  21. Hi @satvik, I believe you can get all of the functionality from the WebPACK version of Vivado (most of us here at Digilent use the WebPACK for most of the work we do). There may be some IPs that require an external license that is not included with WebPACK (or the Design or System edition) versions of Vivado, such as more complex Ethernet or USB IPs from Xilinx. But you would be able to implement a Pmod WiFi with the Cora board; we have an example using the Pmod WiFi with a different Digilent board here as well as a thread on it here and here. Thanks, JColvin
  22. JColvin

    Arty S7 with Simulink

    Hi @xinx_92, Those of us here at Digilent haven't worked with the MATLAB/Simulink integration so we don't have a direct help or advice for you. Based on this page from the Mathworks website in the "Supported FPGA Devices for FPGA Verification" section, it looks like only the Arty S7-25T version has some premade material (with regards to Digilent's Spartan 7 boards). As zygot already mentioned though; Mathworks and Xilinx support and reference materials will be the best resource for you in your endeavor. Thank you, JColvin
  23. Hi @josina, Those of us here at Digilent have not developed any of the Cortex cores with the Digilent boards; any work that exists has been done by Xilinx and ARM. Additionally, I do not think the Cortex M0 has been implemented on an Artix 7, or at least this publication from Xilinx only shows the Cortex M1 and Cortex M3 has been implemented on Digilent boards. I did find some materials working with the Arm M1 and M3 here and here that I would recommend taking a look at. Otherwise, I would recommend asking on the Xilinx forum how you might get the Cortex M0 implemented on an Artix 7 chip. Thanks, JColvin
  24. Hi @satvik, I responded to your other thread here. Thanks, JColvin
  25. Hi @satvik, I apologize for the delay. The reason the Cora Z7-07s is not present in Vivado 2015.4 and 2016.1 is because Xilinx had not added those parts to their software. From what I know, the XC7Z007S chip (the SoC present on the Cora board) was not added to the Vivado WebPACK version until 2016.3. Otherwise, if you are looking to follow Digilent made examples for the Cora Z7-07s, I would recommend using Vivado 2017.4 or 2018.2 as those are the versions of Vivado that we have made examples for the Cora Z7, which you can find in the Cora Z7's Resource Center. Thanks, JColvin