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Everything posted by JColvin

  1. Hi @bhayame, I don't have a Pmod IA on hand and wasn't actually aware that the connectors had a 50 Ohm impedance, though I did confirm that is the case. I believe you would need to add 100 Ohms to the value to get accurate values; it will be a larger impact when calibrating for smaller impedances as discussed on page 30 and 31 of the AD5933 datasheet. Thanks, JColvin
  2. Hi @Rob Frohne, I have moved your question to a more appropriate section of the forum where the engineer most familiar with the Analog Discovery 2 and the WaveForms software will be able to see and respond to your question. Thanks, JColvin
  3. Hi @laurent01, I got it working successfully with lwip on a Zybo Z7-10 on both 2019.1 and 2019.2. The change that I needed to make was leaving the temac adapter settings at auto negotiate (the default); it would then settle at a PHY speed at 1000 and work as advertised. I did not have to make the change that @asmi referenced, though I will be testing microblaze systems next to see if they need it. Oddly and for reasons I did not understand, setting the PHY speed specifically to 1000 rather than leaving on auto-negotiate does not work; I just kept continually getting the repeated Ethernet up, Ethernet down message. Since my board is directly connected to my laptop, I did need to use the static IP address. I recall while at work when I connected to an Ethernet switch that I do not need to set a static IP address. Let me know if you have any questions about this. Thanks, JColvin
  4. Hi @laurent01, I reproduced the issue in 2019.1; I am working on figuring out what needs to be done differently to get working correctly. Thanks, JColvin
  5. Hi @sungwon, That page is intentionally blank, similar to the other USB-UART FTDI solution page missing on our other product schematics. My understanding is that do offer licensing options for our FTDI solution. Let me know if you would like to get in touch with the appropriate Digilent representative to discuss this. Thank you, JColvin
  6. Hi @Mark1, I have sent you a PM with some instructions. Thanks, JColvin
  7. Hi @dudette, Are you using the original Zybo or the Zybo Z7-10? Which version of Vivado are you working with and what do you mean by "it keeps failing"? When you said you have tried the things suggested on the other threads, does that mean you created a new project that only used the UART on the Zynq processor, generated the bitstream, exported the project, and then did the memory test? Thanks, JColvin
  8. JColvin


    Hi @flutnic, Yes, it is possible to do, though I have not personally done this. I took a look and found these two guides from Xilinx on how this might be done here and here. Digilent has a pre-made Petalinux image that ships with the SD card that comes with the board; it's sources are available on our GitHub here. Thanks, JColvin
  9. JColvin

    Type 6 Expanded?

    Hi @KKING, We are in the process of updating the standard; I'll let you know once it goes through. Thanks, JColvin
  10. Hi @laurent01, What version of Vivado/Xilinx SDK are you using? Thanks, JColvin
  11. Hi @[email protected], I will PM you the Digilent contact that will be able to discuss the licensing options that we have regarding the FTDI configuration. I'm not sure what you mean by burn Xilinx FPGA from PC, but if you have a bitstream already created and the board supports it, you could place the bitstream on a flash drive and load it from there. Or if it happens to be a Digilent board, you can load it via the Digilent Adept software. Otherwise, you may just need to use the Vivado Lab Edition. Thanks, JColvin
  12. Hello, I presume you mean the Cmod S6 rather than the Cmod A6. As mentioned in this thread, the Cmod S6 does not have a JTAG header. Thanks, JColvin
  13. Hi @Thejashree, I have asked some other engineers more familiar with our FMC Pcam adapter for their input on some of your questions, but I'll provide some input on the ones that I can. 1) Since 4 cameras are supported through the FMC Pcam adapter, each camera has two pairs of of MIPI lines that are controlled by pairs of pins on the FMC connector. 3) The FMC Pcam Adapter as an adapter does not dictate what lines are broken out the LPC FMC Adapter, that is instead dictated by Vita 57.1. However, the Zynq 7020 devices such as the Zedboard of which we have demos for the FMC Pcam adapter, do not have HP, GTX, or GTH lines, only the HR I/O lines. 4) Unfortunately, our FMC card does not support Zynq Ultrascale+ devices. 6) No camera is included with our FMC Pcam Adapter. The camera that we have tested it with is Digilent's Pcam module: https://reference.digilentinc.com/reference/add-ons/pcam-5c/start. 7) We have not tested it with Sony's cameras so I cannot confidently comment one way or the other on that. 9) The pinout of the FMC Pcam adapter is detailed in it's reference manual here: https://reference.digilentinc.com/reference/add-ons/fmc-pcam-adapter/reference-manual#pin-out. Thanks, JColvin
  14. Hi @brian222, Yes it is possible to do through the Record mode; there are some more details about this available in these forum threads: Thank you, JColvin
  15. Hi @Andy Rabagliati, I have moved your question to a more appropriate section of the forum where the engineer most familiar with the Analog Discovery 2 and the WaveForms software will be able to see and respond to your question. Thanks, JColvin
  16. Hi @dchandra439, The only board that Digilent has with the 2x7 JTAG header is the Zedboard: https://reference.digilentinc.com/reference/programmable-logic/zedboard/start. With regards to the voltage options on the Zedboard, the only way to get 1.8V logic of any kind would be through the LPC FMC header and setting the corresponding VADJ jumper to 1.8V. The FMC header provides 68 single-ended I/O (which can be configured as 34 differential pairs), though you would need an adapter to have them conform to the 2.54 mm pitch spacing. However, the Zedboard (and the other Digilent boards) do not have a header containing 10 I/O pins with a 2.54 mm pitch; all of our Pmod headers only have 8 I/O pins matching that pitch spacing. Let me know if you have any questions about this. Thanks, JColvin
  17. Hi @dchandra439, Digilent has a mix of those features on our boards, though not necessarily all at the same time. There are three questions that I have regarding your specifications: 1) Do your digital I/O pins at the different voltages all need to conform to the connector with the 2.54 mm pitch spacing? 2) For the JTAG cable connectivity, are you looking directly for a 2x7 JTAG header with the 2.00 mm pitch spacing, a small 6-pin header with the TMS, TDI, etc pins, or just the ability to load a bitstream from a host computer? 3) What logic standard is the digital IO at 1.8V and 3.3V conforming to? CMOS? TMDS? Something else? Thanks, JColvin
  18. Hi @2U3, I have moved your thread to a more appropriate section of the forum where the engineer most familiar with the Digital Discovery will be able to see and respond to your question. Regarding the 8ch x 640 x 480 data at 24 MHz that you want to output though; what sort of data is this? Is this 24-bit video data that you want to stream from your PC? Would this be happening at the same time as the recording of the 12ch of data at 24 MHz? Thanks, JColvin
  19. JColvin

    Type 6 Expanded?

    Hi @KKING, I believe we are on board with adding a Type 6A to the standard, though we do have a couple of questions/points that we would like your (or anybody reading this thread) feedback on as a customer. The main drawback against creating a Type 6A at the moment is that if pre-defined GPIO lines are added (I presume you are needing more than two of these GPIO lines since the standard as it currently stands allows for two alternate signals, such as an interrupt and a reset line, to be used in place of the No Connects on pins 1 and 2 on the Pmod header) the ability to daisy chain different I2C modules will become difficult. In principle, if all of the extra GPIO signals were only used on the bottom row of the Pmod header, you could still daisy chain I2C modules by treating the top header row as just Type 6, though that isn't necessarily following the spirit of being able to daisy-chain multiple modules together if you ignore half of the pins. Do you (or anybody else that happens to be reading this thread) have an opinion on this? Additionally, do you think the pass-through pins on header pins 1 and 2 would still be needed on the Type 6A, for the top row or to be included on the bottom row? Thank you, JColvin
  20. Hi @PapaMike, When you say you already have applications using the Arty A7-35, I presume this means you already have the Digilent board files (link to Digilent Github page on them) installed? I just ran a project with the Arty A7-35T on Vivado 2019.2 (I don't have Vivado 2019.2.1 installed), but did not get any critical errors. You can quickly check to see if you have the board files installed by running the TCL command of get_board_parts to see if Arty A7-35T shows up in the list. Let me know if you have any questions about this. Thanks, JColvin
  21. JColvin

    CMOD S6 How to JTAG ?

    Hi @Cris, You can use iMPACT (as well as Adept) to program both the FPGA and the flash. If iMPACT does not detect the board you may need Digilent Plugin for ISE tools, available for download here. Thanks, JColvin
  22. Hi @Amar, Does the last version of Vivado Design Edition no longer work on your machine? Or are you looking to be able to activate newer versions of Vivado? Otherwise, unfortunately Digilent does not sell vouchers for the Design Edition individually as per Xilinx's request. The only way that I am aware of to get access to newer versions of Vivado for the Genesys 2 would be to purchase a second Genesys 2 that includes a voucher. Otherwise, you would need to purchase access to the Design Edition from the Xilinx website. Thank you, JColvin
  23. JColvin

    design digital lock

    Hi @yasmeen, Those us here at Digilent aren't too familiar with Multisim as of yet, though as this is an assignment we would avoid giving a direct solution to this problem. You might take a look at these two projects that I found online here and here though. Neither of them have an alarm or a clock to pulse in the user provided values, but should give you a baseline of something to work with. Thanks, JColvin
  24. Hi @hellgate202, I'm not certain if there is any datasheet readily available yet, or at least that seems to be the case based on this forum thread over on the Raspberry Pi forums: https://www.raspberrypi.org/forums/viewtopic.php?t=272926. Digilent hasn't done anything with that particular camera so we do not have it's datasheet. Thanks, JColvin
  25. Hi @Priya_mp, The folks over on the Xilinx forum will be better able to answer questions on using their lwIP with a Zynq 7045 SoC than those of us here at Digilent. Otherwise, the thing I would recommend looking into is that the pins and voltage levels are correct; if PHY needs 3.3V logic but you are supplying only 1.8V logic, that won't work correctly as 1.8V does not meet the low end of the voltage high threshold. Thanks, JColvin