JColvin

Hi @woldes, One of your hardware boards might already have pull-ups integrated into the PCB if I2C is working on the hardware end of things. The other thing to double check is that you are connecting the correct wires from the AD2 to your circuitry (looks like it should be DIO 2 and 3 from your screenshot). Thanks, JColvin

Hello, I have moved your question to a more appropriate section of the Forum where the WaveForms developer will be able to see and respond to your question with more accuracy than I can provide. Thanks, JColvin

Hi @Ganesh Surampalli, Yes, a voucher to let you use a specialized version of the Vivado ML Enterprise Edition (which lets users create designs for all Xilinx/AMD devices, including the Kintex-325 FPGA present on the Genesys 2 which the ML standard edition does not support) is included with the Genesys 2. For additional information, please see my reply in this post here: Let me know if you have any questions. Thanks, JColvin

Hi @mulzem, The vouchers (provided to Digilent by Xilinx, so they ultimately have the end say on how the vouchers work) have been explained to me to work as follows: For Digilent devices that use an FPGA not included with the free version of Vivado (such as the Genesys 2 with its Kintex-325 FPGA), you will receive a node-locked, device-locked voucher to be able to synthesize and generate bitstreams for designs on a single machine. You can redeem the voucher on the Xilinx Product Licensing site, https://www.xilinx.com/getlicense.html. Rather than locked to a particular version of the software (Vivado Design Suite vs Vivado ML vs HLx vs whatever branding is being used), the voucher is instead time limited for 1 year. During that one year, you will be able to update your Vivado/Vitis install to whatever newest version is available. After the one year period has completed, you will no longer be able to update to newer versions, but you will be able to freely continue to use the existing version that you do have. As for what IPs are available, I believe that all of the regular features (synthesis, ILA, base IPs like Zynq or Microblaze, Clock wizards, etc) are available in both the free Vivado ML Standard Edition and the paid (which the voucher would take of) Vivado ML Enterprise Edition, as per here: https://www.xilinx.com/products/design-tools/vivado/vivado-ml-buy.html. It is specifically the Kintex 325 FPGA that is locked behind the Enterprise/voucher. There may be some IPs that are not included with the voucher nor the free/paid version of Vivado. For the Genesys 2 specifically, this would be the Gigabit Ethernet PHY (TEMAC IP) and the DisplayPort IP licenses; https://digilent.com/reference/programmable-logic/genesys-2/reference-manual#software_support. If you wish to use these IPs beyond their own separate evaluation periods, you would need to pay Xilinx for them, same as Digilent would have to. From my understanding, all other "standard" IPs are freely included with Vivado. If you want to know the specific status of an IP, say Clocking Wizard, you can search for it on the Xilinx website and see if it is bundled with Vivado (as opposed to having an option to evaluate the IP). I believe you should be able to transfer the license to a different machine. This is covered in the last question in Section 8 in the Xilinx/AMD FAQ on licensing, https://www.xilinx.com/products/design-tools/faq.html, "What happens when a license machine "dies" or is replaced". Again, Xilinx will have the end say on how the vouchers will specifically work (though I imagine the licensing site will also explain what you are getting before it uses the voucher), so any specific functionality questions I would recommend you ask Xilinx about. I do not have a license nor a Genesys 2, so unfortunately I do not have any specific experience to share. Let me know if you have any questions. Thanks, JColvin

Hi @Dniel.Schmid, This will correspond to the line item of s25fl128sxxxxxx0-spi-x1_x2_x4 The correct part is noted in the Reference Manual, https://digilent.com/reference/programmable-logic/nexys-a7/reference-manual#quad-spi_flash, but it looks like the callout for what to select in Vivado has not been updated to the names that Vivado now uses. I see about updating that. Otherwise, what I would personally do if you can't find a listed Manufacturer in the dropdown by looking up the part's official datasheet (as is the case for the S25FL128SAG since Cypress bought Spansion and apparently somewhat recently Infineon acquired both Spansion and Cypress) would be to simply start typing the letters of the module in the search bar to see what comes up to help narrow down your results. Or just do what you did and get a reply from a representative of Digilent. Let me know if you have any questions. Thanks, JColvin

Hi @JPierce, I apologize for the delay. I received confirmation that, as of writing, Digilent has over 200 pieces of both the SMT3 and SMT4. I don't have any insight into the distributor side of things regarding their lead times/lack of stock; I'm not involved with that end of the business. Thanks, JColvin

Hello, I have moved your question to a more appropriate section of the Forum. Thanks, JColvin

Hi @shaur, I have not heard of any updates as of yet for the the OOB for the Genesys ZU for 2023.1, but I have reached out to double check. Thanks, JColvin

Hello, I have sent you a PM with some additional instructions on how you can restore the FTDI chip. Thanks, JColvin

Hi @Evan Cleary, I do not have LabVIEW installed, so unfortunately no, I do no not have any real insight into the broken wire. From my limited experience and memory, that's usually indicative of mismatched data types. If simply deleting the wire and then reattaching it does not work, I would probably be looking to break up the cluster to see if I can "route out" (I don't know what correct jargon would be) the one expected data type. Thanks, JColvin

Hi @yildizabdullah, I have sent you a PM with some instructions on how to recover the JTAG HS2. Thanks, JColvin

Hi @binhkieudo, I have sent you a PM. Thanks, JColvin

Hi @lhphuc_mrvl and @Hernanrl1, I have sent you both a PM with some instructions. Thanks, JColvin

Hi @Yuko Yamamoto, Your layout seems fine. What I am not certain of is what you mean by the writing of the board name and other details to the EEPROM. With the Digilent JTAG modules, you should only need the cable drivers -- accessible either through the select versions Xilinx has as part of installation (https://support.xilinx.com/s/article/59128?language=en_US) or the latest version of the runtime drivers directly from Digilent here: https://digilent.com/reference/software/adept/start. The Xilinx/AMD software via the Vivado hardware server should then be able to detect the downstream FPGA. If the host computer can no longer correctly identify the module (an example of what you should see for Windows is in this thread and for Linux in this thread), then I can help you get the JTAG SMT3 configuration reset. Thanks, JColvin

Hi @Evan Cleary, I do not believe there is a way to access the DMM from the Digilent LabVIEW VIs and at least as of yet have not heard any plans to There is an existing Python example that uses the DMM on the ADP5250 (AnalogIO_ADP5250_DMM.py); you can find it in the samples folder alongside the PDF version of the WaveForms SDK Reference Manual; you can readily open this folder from the Welcome tab of the WaveForms application. Alternatively, if you happen to have existing VirtualBench VI material that runs the DMM, you can replace some drivers to make it work with the ADP5250 as mentioned in this post and the one immediately following it: The catch with this, of course, is that this is technically a work-around as opposed to an official workflow. Let me know if you have any questions. Thanks, JColvin

Hi @Takashi "The Yaka mein", I have sent you a PM with some additional information. Thanks, JColvin

Hi @Takashi "The Yaka mein", I reached out to the Engineering Services Manager about this last Friday. I will follow up again today to hopefully learn an update. Thanks, JColvin

Hi @jcanion, The 12 V variant of the PowerBRICK could be powered by the +5 V supply of the Analog Discovery 3 to then provide both +12 V and -12 V to other components on a breadboard. The output current for each rail is 100 mA, but if you are just needing a 12 V reference so that your amplifier does not clip on the edges then this should be okay. At the very least it cheaper than getting an Analog Discovery Studio which has +/- 12 V as one of its fixed rail supplies, and probably less janky than getting an entirely separate wall wart 12 V power supply and an adapter for the barrel end. Let me know if you have any questions. Thanks, JColvin

Hi @JAlaj, The Digital Discovery has enough pins to support this, though with so many separate devices that are being driven by the clock and controller out peripheral in (MOSI) lines, I would image that the drive strength of the signal would start to become a concern as well. However, it is my understanding that the Multi MISO option is only available in the Spy sub-tab for the SPI function within the Protocol instrument. Ostensibly, it may be possible to do some sort of custom setup where you have the Logic Analyzer continuously capturing data on the 32 MISO lines and then a separate Pattern Generator instrument running a custom pattern controlling the remaining three SPI control signals to tell all the peripheral devices to periodically take a sample (or whatever function the peripheral devices are doing), but I have not attempted such a large scale setup. Thanks, JColvin

Hi @ryoryo10, I might be mistaken, but I don't believe Digilent has defined this particular parameter. I likely did not do a proper setup or test, but with the AD3 at my desk outputting a 40 kHz clock from one of its channels, this is what I measure on the ADP2230 oscilloscope (using a different instrument purely to show a different internal oscillator being used for timing) after over 5000 acquisitions at 100 MHz sample rate (with the default 32768 sample per acquisition size, this works out to about 65k 40 kHz pulses being analyzed): When the precision is scaled to the 1 mHz level (the first row in measurements), I get (to be clear, with a single AD3 on a singular hardware setup) an average measured frequency of 39,999.669 Hz, or -8.275 * 10^-4 % less than a precise 40 kHz. When I ran a similar setup (again, one unofficial, probably poorly setup singular test on a singular hardware setup) for a 1 MHz digital square wave, the difference between the measured average and the theoretical was very similar at -8.273 * 10^-4 % less, though the measured minimum and maximum were less close when compared to the 40 kHz counterpart. Let me know if you have any questions. Hope this helps, JColvin

Hi @Takashi "The Yaka mein", Yes, this voucher should have been included with the Genesys 2. If I remember correctly, this would be on a piece of paper that is inside the Genesys 2 cardboard box. If this voucher was not in the box for the new product, then I will look into this and work with you to get this resolved. Thanks, JColvin

Hi @digitalone, For the split termination setup that is used on the Pmod CAN (both ends terminated if they are the ends in your system), my understanding is yes you will want to use JP2 to enable the capacitor load, at least based on this TI App Note (section 4.5.2), https://www.ti.com/lit/an/slla270/slla270.pdf, which is also reiterated in this Technical Article from TI here, https://www.ti.com/document-viewer/lit/html/SSZTB40. Let me know if you have any questions. Thanks, JColvin

Hi @digitalone, They should be able to be connected directly together without issue via a RS232 cable, yes. Each Pmod CAN has a jumper (JP1) to optionally enable the 120 Ohm termination between CANH and CANL, as well as an additional JP2 jumper to optionally terminate the lines with a capacitor to ground. You can see the setup in the Pmod CAN schematic, https://digilent.com/reference/_media/reference/pmod/pmodcan/pmodcan_sch.pdf, which can also be found on the right-hand side of the Pmod CAN Resource Center: https://digilent.com/reference/pmod/pmodcan/start. Let me know if you have any questions. Thanks, JColvin

Hi @tm_c, I have not been able to convince the key stakeholders as of yet to post a 3D model or official dimensional drawings, but after a bit of searching I did learn that the drawing @SINAPTEC COMBLEZ used is an official one that was originally posted by the WaveForms developer about 4 months earlier in this post, https://forum.digilent.com/topic/26785-analog-discovery-3-dimensions/#comment-81182, so I can at least confirm that the listed dimensions on that drawing are accurate. Thanks, JColvin

Hi @Neil22, I agree that the two boards are suffering from a manufacturing defect. Please send me a private message with the Digilent order number Haley Tech made with the purchases and purchase date if it is different from what you listed in your original post (you already provided the serial number) and I will get the information to our Sales team who will help process the replacement. Thanks, JColvin