JColvin

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Everything posted by JColvin

  1. Hi @brunomaximom, You would still be able to do C programming from MPLAB X; the catch is that you need additional hardware in order to do this as @Cristian.Fatu mentioned. Thanks, JColvin
  2. Hi @sab, I took a look online and found this Xilinx thread as well as one of Xilinx's User Guides as referenced by zygot that should be of help to you regarding the Worst Negative Slack. The maximum frequency (presuming you are talking about how fast your design will work) will not be related to the worst negative slack; it will depend on how your design has been implemented. The DC and AC Switching Characteristics on each of the respective chip's 7-Series datasheet will give you some maximum speeds; however since your design will inevitably not solely dedicated towards the singular task of getting one clock working at full speed, I would expect something more along the lines from this Xilinx thread. Every design will be different though. Thanks, JColvin
  3. Hi @thoriam, Could you provide a picture of your physical setup so that we can help better determine what the problem might be? Thanks, JColvin
  4. Hi @Duncan.Wu, Welcome to the Forums!
  5. Hi @chainastole, Re-reading through this thread and the Xilinx thread, you likely do not need the board files as they exist for "normal" Vivado, because as @AndrewHolzer mentioned My understanding with HLS is that you would be able to create all of your needed IPs in C or C++ rather than in HDL or through pre-made IP cores, so the purpose of creating a Digilent board entry in the VivadoHls_boards.xml is to ensure the correct FPGA (or SoC) is being targeted while creating your design. The rest of the board files add other conveniences (such as per-configuring the design for the on-board DDR memory) but that is a not a required component. Thanks, JColvin
  6. JColvin

    Cmod A7 HW Target Shutdown

    Hi @tim1, Could you clarify what issue you are encountering with your Cmod (presumably A7)? Thanks, JColvin
  7. Hi @RKM, I apologize for the delay. Which board do you have and what do you see when you attempt to connect to it with the Digilent Adept software? Thanks, JColvin
  8. Hi @Robert R, I haven't received my S7-50T as of yet, but you do not need to attach the entire timing report; a screenshot of the Problems or Timing tab (located by default in the bottom center of the Vivado GUI) will suffice for the moment. And to confirm, after creating the block design and the associated wrapper, does the project successfully generate a bitstream in addition to the verification, synthesis, and implementation that you mentioned? Thanks, JColvin
  9. For others viewing this thread in the future, we responded to the users other thread here:
  10. Hi @zz-2500, I apologize for the delay; I am taking a look into this, though I haven't been able to replicate this exact error. One thing I would try would be to right-click on the sdcard_bsp and choose to regenerate the BSP source files since that can help resolve a lot of compilation errors that occur while the project is being generated. Additionally, when you created the empty application project, did you make sure to set it as a C++ (rather than the default C based project) as per the Pmod SD IP readme? Thanks, JColvin
  11. Hi @ad2user2019, @attila will be better able to comment on the hardware side of things with regards to what might have happened, though I am a bit surprised it happened during the powering down sequence since that isn't usually associated with current spikes or something similar. As an additional check, are you able to see the Analog Discovery 2 within Digilent's Adept 2 software? On a Windows system, are you able see that the Analog Discovery 2 is plugged in when looking at the Device Manager? This post here has a nice list of possible options and what to expect to see in the Device manager. Let us know what you find. Thanks, JColvin
  12. Hi @Takashi "The Yaka mein", I apologize for the delay. I am not certain why that particular power supply is not included for the Japan export version of the kit that Xilinx makes. Your guess that it could be a certification issue would make sense, though I do not know this for certain since that particular power supply isn't sold directly on our website as per this forum thread here. I will ask and find out if somebody at Digilent happens to know the reason the power supply would be excluded from the Japan export version, though it may be better to reach out to Xilinx as they are the ones who made that choice for their kit. Thanks, JColvin
  13. Hi @Ondrej, Within the WaveForms GUI do you receive the same "Device is not communicating" message if you happen to select other tests (there is a screenshot showing on this particular comment here: And to confirm, after you restore the factory settings, the device (oscilloscope channels, function generator, etc) all work as expected until you go through the calibration process again? Am I interpreting this correctly? Additionally to confirm, when you said "both probes measured a few kilovolts...", are you just using the two oscilloscope flywire channels or are you using actual probes via the BNC Adapter? Thanks, JColvin
  14. Hi @HeshanS, I do not know this for certain but I think the chip was setup so that the zero setting for acceleration was while the module is in free fall. So when the module is motionless it senses the standard 1g acceleration due to gravity. Again, I'm not an expert in the physics side of things regarding the left handedness vs right handedness, but I suspect it won't be as simple as simply inversing the coordinate values. I don't have much more advice for the math side of things unfortunately. Thanks, JColvin
  15. Hi @Devendra Pundir, I apologize for the delay. I am a little confused about the situation you described. If I understand it correctly, the Vivado Hardware Manager is able to detect the JTAG HS2 and your custom FPGA board downstream from the JTAG HS2, but the Vivado Hardware Manager is not able to recognize the JTAG SMT2 NC and the downstream FPGA? Thanks, JColvin
  16. Welcome to the forums @ichibrosan!
  17. JColvin

    CAN Bus

    Hi @tahoe250, Have you taken a look at these three threads (one of them is the same that Notarobot linked to)? I know from these materials the Pmod CAN IP core ended up getting updated to a newer version that correctly gets the Pmod CAN (presuming that is what you using on the Pmod CAN). Additionally, attaching your block design rather the zynq configuration would be more helpful. Thanks, JColvin
  18. Hi @chainastole, Where are you seeing this Vivado HLS lab that was created for the Zedboard? I can say that I am not aware of a Digilent-made tutorial and can confirm that we do not have any pre-built board files for Vivado HLS. As per the Xilinx thread that both you and jpeyron linked to, you can make the Arty board visible during the board selection screen in Vivado HLS, but as there are no board level constraints it will not be of any real use. Thanks, JColvin
  19. Hi @rickwills, I don't have any NI USB boards to test this for myself, but based on this thread, I think you will just need to find the correct driver for them as the LabVIEW Home Bundle probably doesn't have that driver pre-installed for you. And to clarify, LabVIEW Home has the same features as LabVIEW full (not a reduced set like the LabVIEW Student edition); the limitations instead come in the form of licensing (Home Edition Addendum and NI General Purpose Software License links) and the fact that not every extra module is compatible with the Home Edition, such as the FPGA module not being compatible with it. Thanks, JColvin
  20. Hi @Robert R, When you create a block diagram based off of the Digilent board files, Vivado will automatically generate the appropriate details it needs for constraints when Vivado is going through the synthesis process. You do not need to add in a constraints file yourself to define any of the clocks or IO pins that you are using in a block design. Adding in your own .xdc can easily create conflicts if any of the names end up different. However, if there were any pins you wanted constrained that you did not address or use in your block design, you would want those pins individually constrained within a .xdc. I'm waiting for my own Arty S7-50T to arrive to verify things for myself, but could you provide a screenshot or text of the timing errors you are receiving? Thanks, JColvin
  21. Hi @sgrobler, I am able to successfully connect to my phones WiFi hotspot on firmware 1.3.0. I get the same message pop-up as you regarding the firmware update required, but I click the "OK" option and then select the Instrument Panel where-upon am I greeted with the same message, choose OK again, and then I am brought to the Instrument Panel where I am able to successfully run the OpenLogger. I do agree though that the pop-up message should not be occurring though. I have reached to @AndrewHolzer to help address this. Thank you for the feedback, JColvin
  22. Hi @HeshanS, I'm not a physicist, so I don't know the terminology perfectly, but it is my understanding that an accelerometer measures deviations a static (non-moving) environment. Since z-axis is pointing vertical direction for a positive, because when the accelerometer is not moving it is essentially applying 1g upwards (via the normal force from the surface it is sitting on) counteracting the standard 1g in the downward direction from gravity. If the sensor was in freefall, 0g would be measured since it would be in a true "standard" environment. This is explained a little more in section 2.6.2 with their definitions of zero-g and other situations. Thanks, JColvin
  23. Hi @Avin, Our programming solution only works for Digilent made boards; which FT232 device do you have? Thanks, JColvin
  24. Hi @Devendra Pundir, The solution that we have is only compatible with Digilent devices. Does your custom board contain a Digilent chip like one of our JTAG boards? If so, what do you see when you connect to the Digilent Adept software? Thanks, JColvin