JColvin

Hi @Yatharth Gupta, DDR memory on Zynq based boards are connected directly to the PS, so you do not use a mig.prj like you would for a non-Zynq 7-series board. Presuming you have the Digilent Board Files installed (either via this method, https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files, or by installing them via the Xilinx Board Store when initially choosing a part upon creating a project), after you add the Zynq processor to your block design, run block automation and leave the Apply Board Preset checked, and the DDR memory will be connected for you; https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_a_processor_to_a_block_design. Let me know if you have any questions or if I am misunderstood what you are wanting to do. Thanks, JColvin

Hi @Jana Saleh, The Digital Discovery is not able to use an external clock but does have a Sync mode which may be helpful for you. Check out these two threads for more information: Let me know if you have any questions. Thanks, JColvin

Hi @Tparng, Since you didn't directly clarify this, do you have the Vivado Hardware Manager open at the same time and connected to the Zedboard at the same time while trying to configure it through djtgcfg? This would be a point of failure if the JTAG access was otherwise already claimed. Otherwise the Adept developer clarified to me that Adept should be able to program the PL of the Zynq 7020, but this has not been thoroughly tested. Adept is not able to configure the PS (or flash memory in general for non-Zynq devices). Let me know if you have any questions. Thanks, JColvin

Hi @janpi, I'm not Attila of course, but this is what I get for Channel 3 with no probe or shorting: The offset appears to be different than yours, but is otherwise of a similar magnitude. Thanks, JColvin

Hi @Matias Aguirre, The two products are identical in hardware design. There is a similar thread on this topic here: Support for Ettus boards is best done through the Ettus mailing lists where you will get the most direct support from the engineers who are most experienced with the Ettus products: Let me know if you have any questions. Thanks, JColvin

Hi @diminDDL, All of Digilent's material on GitHub, unless otherwise stated directly in the repository/code itself, uses the MIT license: https://github.com/Digilent/licenses/blob/master/mit/License.txt. Let me know if you have any questions. Thanks, JColvin

Hi @Mani, I believe the most recent Petalinux build for the Eclypse Z7 is 2019, at least based on the material here: https://github.com/Digilent/Eclypse-Z7-OS. In terms of adding I2C support, you'll want to add an I2C driver to your Block Diagram within Vivado alongside the Zynq Processor. After you have all of the supported material that you want enabled, you can then export the .xsa and build your BSP within Petalinux based off of that. There is a small guide on adding I2C to an intended Petalinux design here: https://www.adiuvoengineering.com/post/microzed-chronicles-petalinux-i2c-in-the-ps-and-axi-iic, as well as some additional material on creating your own .xsa / BSP file available here: https://forum.digilent.com/topic/27087-creating-xsa-file-for-petalinux/. Let me know if you have any questions. Thanks, JColvin

Hi @dmangione, I believe that the Eclypse Z7 will always show up with a serial number of all 0's (or at least Eclypse Z7 is listed out in an identical fashion); the output from your Enumerate shows a device is detected. Have you tried running some of the samples that are built in to WaveForms? I am able to successfully run any of the examples that are available in there. It looks like the GitHub WaveForms SDK material (separate from the built-in material) does not have the Eclypse Z7 as a supported device: https://github.com/Digilent/WaveForms-SDK-Getting-Started-PY/blob/master/WF_SDK/device.py#L149. I will see about getting this corrected and future proofed as this will inevitably need updated again as Digilent continues to make new products that are compatible with WaveForms. Thanks, JColvin

Hi @adoc, Yes, once you have the .bit file from Vivado you can export the .xsa from Vivado (this step in the Baremetal Software Guide has some additional detail https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#export_a_fixed_post-synthesis_hardware_platform), and then create a Baremetal Boot Image which you can load either onto flash memory or the microSD, both of which have instructions available here: https://digilent.com/reference/programmable-logic/guides/zynq-baremetal-boot. Let me know if you have any questions. Thanks, JColvin

To add on to this, Attila did try to add a reference clock output to the AD2 to enable the AD2 + AD3 Dual Mode possibility (as per the last post in this thread: https://forum.digilent.com/topic/26663-dual-mode-ad2ad3-potential-implementation/) but there was not room within the FPGA for this additional logic.

Hi @Dan lee, The SMA to Alligator clip cable itself will readily support direct current or alternating current. Please check with with host board's manufacturer that this SMA cable will connect to for what type of current it supports. As I understand it, the lowest voltage specification for the cable would be the red and black wires (UL1015 18AWG) that are rated for 600 Vac or 750 Vdc. Let me know if you have any questions. Thanks, JColvin 250-086 SMA to Aligator.pdf

Hi @Fresnel7, Check out this Forum thread for more details on this: Let me know if you have any questions. Thanks, JColvin

Hi @SimonKFra, Yes, the two individual solderless breadboards both have adhesive backing that you peel the protective cover off so that they can be adhered onto the Blank Canvas. Thanks, JColvin

Hi @JamesVP, Digilent is a wholly owned subsidiary of NI; https://digilent.com/shop/company/. As for your other question, the Analog Discovery Pro ADP5250 is effectively a reskinned VB-8012. The wireless functionality was removed and the device is only usable with WaveForms in Windows (unless you replace some DLLs to have it work in LabVIEW, https://forum.digilent.com/topic/24267-adp5250-and-vb8012-question/#comment-71623), but the underlying hardware specifications are the same (aside from some software enhancements such as to increase the maximum frequency of the square and ramp waveform generation from 5 and 1 MHz to 20 MHz each): https://digilent.com/reference/test-and-measurement/analog-discovery-pro-5250/specifications. Let me know if you have any questions. Thanks, JColvin

Hi @Stefan C, I am waiting for a Rev D of the Arty Z7 to come into the office so I can test this as I only had Rev B's on hand. What version of the Xilinx tools are you using so I can better attempt to replicate your setup? Thanks, JColvin

Hi @HowardN, That is interesting me that there isn't a part selection for the Kintex 325T considering that Xilinx sells their own development board that also uses the 325T chip (the KC705 Evaluation Kit). I only have the Standard ML edition for 2023.1 but I am able to see and select the xc7k325tffg900-2 part both from the general Parts list and the Genesys 2 from the Boards list (after refreshing the catalog) since I had the Kintex 7 parts box checked during the Vivado/Vitis installation. If you also have the Kintex-7 parts included as part of your initial installation, then I am not certain why the part would not be showing up as a selectable option. Thanks, JColvin

Hi @HowardN, I don't have a license for the Genesys 2 for more recent versions of Vivado to be able to test this out though I'm not certain why it says you are unable to access the Genesys 2; I was under the impression the license just enabled bitstream generation; the Kintex 325T part selection is dependent on FPGA parts you have installed and you can freely add parts to your install via the Xilinx Information Center application (which comes with Vivado/Vitis) in its Manage Installs tab. If the Vivado License Manager / Xilinx Information Center applications don't let you manage the license in the way you are needing, nor the Xilinx Product Licensing Site (https://www.xilinx.com/getlicense, taken from https://www.xilinx.com/support/licensing_solution_center.html) then I would recommend posting on Xilinx's Licensing Forum, https://support.xilinx.com/s/topic/0TO2E000000YKXwWAO/installation-and-licensing?language=en_US, to get a more direct and accurate answer than Digilent can provide as Digilent does not create or handle the licenses, we just obtain them from Xilinx to go with products that need them. Thanks, JColvin

Hi @Jiri, I am not familiar nor have used the MATLAB flow so further questions about the connectivity and process flow would be best directed to MATLAB for the most accurate answers, but in terms of connecting over JTAG for FPGA-in-the-Loop you just need to use a microUSB cable as per the JTAG Connection Requirements table for Xilinx devices on the MathWorks site here: https://www.mathworks.com/help/hdlverifier/ug/what-is-fpga-board-customization.html#bt72ftg-1, since the Arty S7 already has an on-board USB-JTAG module implemented on it. Thanks, JColvin

Hi @bloggins666, You are correct that the Baremetal tutorial (https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi) XSA would only set up material for what is present in the Block Design; in this case the ARM processor, the 4 buttons, and the 4 LEDs. If you wanted to have access to all of the I/O pins on the PL side (and maybe anything extra on the PS side that isn't in the default configuration), you would need to create the associated design in Vivado, generate the bitstream for it, and then export the XSA which you would then import into Petalinux. Adding access to the most of the other GPIOs will be fairly trivial. Simply add the Arduino styled headers and RGB LEDs to the block design as done for the LEDs in first part of the Adding GPIO Peripherals step (https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_gpio_peripherals_to_a_block_design). When right-clicking on each component in the Board tab to Connect Board Component, I would choose to create a new AXI GPIO IP (rather than an existing one). The second bit of that tutorial that shows how to manually assign pins is mostly there to show an alternate design flow within Vivado. For connecting things like the HDMI ports, what I would personally do is to take the existing hardware design of the Arty Z7-20 HDMI input demo (https://digilent.com/reference/programmable-logic/arty-z7/demos/hdmi-input) and then add in the other GPIO pins like I described in the above paragraph. Once the bitstream is generated and the .xsa is exported from Vivado, you'll be import it into Petalinux and create the BSP via petalinux-config if memory serves me. I've linked some additional resources on how this might be done in this post here: Let me know if you have any questions. Thanks, JColvin

Hi @bloggins666, No guide update yet, but letting you know that Digilent will be working on getting the guide updated within the next few weeks, hopefully by the end of November (the usual corporate resources/people having to wear multiple hats constraint strikes again); my co-worker got a project successfully created and launched an application in 2023.2, but noted that the step-by-step flow is quite different and the guide update is definitely needed. FWIW, they weren't able to get the --classic parameter to work via the Windows command line, but maybe Linux will have a different result. Thanks, JColvin

HI @C7AuD10, I have not heard of this particular type of failure before. The DONE LED (LD6)only lights up when the on-board FPGA determines that it is configured and outputs the appropriate active signal to enable that LED. The default boot configuration of the Cora Z7 (no jumper block loaded on JP2) would be over JTAG as there is a pull-down resistor on the two associated MODE pins (page 7 on the schematic, https://s3-us-west-2.amazonaws.com/digilent/resources/programmable-logic/cora-z7/Cora+Z7_sch-public.pdf), which does not automatically configure the board. All this to say that I don't have any insight on what might have happened to the board to get it into this state. The regulator heating up quickly is certainly not good of course, but that is (as far as I understand) completely isolated from the state of the DONE LED. Vitis also doesn't have any sort of control over this behavior as well to get it into a non-functional fail state. I would recommend to get the board replaced. If you purchased the board directly from Digilent, send me a private message with: - Board Serial number (underside of the board on the barcode sticker starting with DA) - Order Number - Purchase Date - preferred email So I can get the RMA process started with our Sales team. They will contact you for any additional details they need that I don't have access to (such as shipping address). If you instead purchased the board from a distributor (Newark, Amazon, etc), you will need to contact the distributor to determine their replacement process; they will then contact Digilent separately for their own RMA. Feel free to point them to this thread as evidence of having worked with Digilent. Thanks, JColvin

Hi @Sai Teja Palla, This thread should help you: Thanks, JColvin

Hi @bloggins666, I took a look at the Vitis Release Notes (https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html) for 2023.2 that were published yesterday that there is a new GUI within Vitis. I don't think anybody at Digilent has gotten a chance to download 2023.2 yet, but considering that AMD/Xilinx is listing the new GUI as the first bullet point of highlighted features, we'll be sure to get the Baremetal Software guide updated as appropriate. Thanks for the heads up, JColvin

Hi @kkcheon, What revision of the Zedboard do you have and what files are present on the SD card that came with the Zedboard? They should be matching the materials in the sd_image folder that is within the Out of Box demo available on the Zedboard Resource Center here: https://digilent.com/reference/programmable-logic/zedboard/start#additional_resources. Thanks, JColvin

Hi @s.gafoor, I'm not certain what other SD card files you might be referring to. Did the Zedboard not boot up as per the instructions in the readme file that was included in the sd_image folder? Thanks, JColvin