JColvin

Hi @Nick Conklin, The datasheet for the embedded ADC081S021, specifically section 8 and Figure 2 in section 7.6 https://www.ti.com/lit/ds/symlink/adc081s021.pdf, will be of the most help for figuring out how the TI ADC organizes it's data. Many years ago (clarifying this detail since this document isn't linked on the resource center nor been looked at for accuracy), I wrote a bit of extra information on how the 8-bits of usable data are organized in the 15 bits of data from the ADC here: https://digilent.com/reference/pmod/pmodals/user-guide#communication_protocol, though I think I replicated this information in the Interfacing with the Pmod section of the Reference Manual, https://digilent.com/reference/pmod/pmodals/reference-manual. Regardless, I do not disagree that the information is hard to parse. I will see about getting some sort of timing diagram into the reference manual if I get the opportunity. Thanks, JColvin

Hi @Simon Koops, Unfortunately, there really isn't one outside of getting the XUP USB JTAG programming to work on newer Windows. There are a number threads discussing this: https://forum.digilent.com/topic/26104-programming-xilinx-cpld/ https://forum.digilent.com/topic/158-programming-cplds-with-hs1-or-hs2/ https://forum.digilent.com/topic/23686-program-cpld-with-xup-usb-jtag/ https://forum.digilent.com/topic/350-jtag-usb-versus-jtag-hs2/ However, the XUP USB JTAG does work on Windows 10, though it's been a few years since I've specifically tested this out. Let me know if you have any questions. Thanks, JColvin

I have sent some PMs. Thanks, JColvin

Hello, Yes the Vivado Hardware Manager will automatically claim JTAG access over Adept to the JTAG HS3 (and other Digilent JTAG programmers). You would have to the Vivado hwserver.exe closed in order for the JTAG HS3 to remain connected to Adept or a non-Vivado solution. As for the serial terminal portion, the JTAG HS3 does not support a serial terminal connection where you can have UART data be sent over the module, https://digilent.com/reference/programmers/jtag-hs3/reference-manual. You would need a different module that supports such connections, such as the JTAG SMT3, https://digilent.com/reference/programmers/jtag-smt3/reference-manual. There is a way to use BSCAN primitives to get serial data over JTAG lines within Xilinx SDK/Vitis, but Digilent does not have any support for getting this working within the Xilinx software suite. Let me know if you have any questions. Thanks, JColvin

I have sent you a PM.

It looks like Petalinux wasn't able to access a number of different repositories, which can happen for a variety of reasons. I'm not certain what issue might be in your situation specifically, but here are a number of other threads that might help you find the source of this: thread1, thread2, thread3. Thanks, JColvin

Hi @Tparng, I apologize for the long delay. I'm not certain why djtgcfg is not successfully configuring the Zedboard. It's not particularly helpful to you, but I am able to successfully configure the Zybo Z7-20 I have on my desk with the Adept GUI (which I was told by the developer uses the same underlying API calls that djtgcfg uses). Is there a particular reason that you want to use dtjgcfg when Vivado is already working to configure the board? Thanks, JColvin

Hi @John J, If the two boards are showing different behaviors with the same .bin and based on everything else you have tried, I am inclinded to think that there is some sort of hardware error on the board and that you should work on getting it replaced. If you purchased the board directly from Digilent, please private message me the following information: - Order Number - Purchase date - Serial number of the board (on the barcode sticker that starts with "D") - Preferred email contact so that our Sales team can follow up with for any additional information that I don't have access to (such as confirmation of shipping address) If you instead purchased the 3EG from a distributor (such as Mouser or RS Components), you will need to contact them for their own RMA process. Let me know if you have any questions. Thanks, JColvin

Hi @ds2329, I asked some of my co-workers and we were not able to replicate this with the Zybo Z7-10's or -20's we had on our separate desks on the 2022.1 or 2023.1 release of the Pcam 5C project. Because you are getting some sort of image, this is indicative of one of three main problems. 1. HDMI Output cable or port is faulty. Unlikely as you are getting an image, but you can easily test for this with the Zybo Z7 HDMI demo, https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi. 2. The ribbon cable is not properly seated or is damaged. I know the cable should be oriented correctly as you would get an error and no output at all if was plugged in backwards, but I would double check that the cable is secured properly on both ends (lift the plastic tab, insert the cable, push the plastic tab back down) as well checking to see if the cable is creased or if any of the contact pads at the ends of the cable have been worn off. 3. The Pcam 5C is faulty. This is the hardest to eliminate, mostly because it requires having a secondary Pcam 5C & ribbon cable (and second Zybo Z7 board for the sake of testing) to determine this. Questions that I have for you would be as follows: - What are the results of questions 1 and 2 from above? - Has the Pcam 5C been used (successfully) before? - What revision of the Pcam 5C and the Zybo Z7-10 do you have? Thanks, JColvin

Hi @ds2329, We are taking a look into this; I am able to successfully get the 2023.1 release version of the demo to run on my Zybo Z7-10 as is (both with the Vitis release and importing the existing Vivado .xsa into Vitis), but as you indicated (other thread) there are too many users where this demo is not working on their boards. Thanks, JColvin

Hi @John J, The engineer who most recently worked with the Genesys ZU QSPI flash (thinkthinkthink) is out of office for longer than I expected, though I was asked to clarify the following information: Are the two Genesys ZU 3EG boards using the same file programmed into them, or are the running different projects. You were already on this thread from before, https://forum.digilent.com/topic/26069-unable-to-flash-qspi-vivado-rev-20221-5ev-eval-board/, and the engineer I talked to hasn't observed teh XFSBL_ERROR_INVALID_EFUSE_SELECT on the Genesys 3EG, but did you happen to try the QSPI x2 workaround that got mentioned at the end of the thread? If you encountered this error with the same file programmed into both boards QSPI flash memories and the x2 mode workaround is not working, some further investigation will be needed. Let me know what you learn. Thanks, JColvin

Hi @Leon18, As @zygot indicated, there is no firm rule on the amount of current a Pmod is allowed to draw from a host (outside of the assumed not needing to draw more than 100 mA). Looking at Table 20 within section 2.11 of the Zedboard Avnet User Guide (available here: https://digilent.com/reference/programmable-logic/zedboard/start#documentation), they have a generic estimate of 3 A being allocated to the 5 Pmod ports and the FMC connector. Discounting 2 A to the FMC connector (as that is based on whatever you have VADJ set to), this supposedly leaves around an amp between the 5 ports. Of course, there isn't anything physically stopping the end user from attempting to draw more current from any of the voltage rails, nor will that Table 20 perfectly reflect whatever design you have implemented. Let me know if you have any questions. Thanks, JColvin

Hi @Mani, No, you will not be able to port the zc702 to the Eclypse. The main reason for this is that although they both use a Zynq 7020 chip, the pinouts and settings to the different peripherals (buttons, DDR, etc) are very likely not going to match between the two boards, making them incompatible. You can create your own BSP within PetaLinux, as per the details mentioned in this thread: https://forum.digilent.com/topic/27087-creating-xsa-file-for-petalinux/. Unfortunately, you would not be able to back-port the .xsa from 2023 to an older version of the tools as backwards compatibility is not something typically available within the Xilinx tool suite. Referencing your other thread, .xsa and .hdf files are "basically" the same as far as the end user is concerned, but Xilinx tools will make a distinction between the two I do not know if QEMU is integrated with the 2019 Eclypse Z7 BSP. I will ask the engineer more experienced with Petalinux about this. Thanks, JColvin

Hi @Ahmad Mansour, 1. Yes, GPIO connections are what you will want. You can verify the pinout style matches what you want on page 17 of the SP701 schematic. 2. Based on the Timing Characteristics table of the embedded AD5541A datasheet, https://www.analog.com/media/en/technical-documentation/data-sheets/AD5541A.pdf, the maximum SCLK frequency for 3.3 V logic is 50 MHz. Be sure to account for the output voltage settling time that is referenced in the AC Characteristics though (Table 3 of the same datasheet), as that will impact your effective output rate. 3. No, Digilent does not have such an-add on Pmod module that combines both an DAC and ADC (though there is a Pmod AD1, Pmod AD2, and Pmod AD5). For a more 'all-in-one' style solution, I would likely be recommending either the Analog Discovery 3 or the Eclypse Z7 in combo with the Zmods of your choice. Let me know if you have any questions. Thanks, JColvin

Hi @Fadi, I have configured the Arty A7 through the 6-pin JTAG connector (J8 on the underside of the board). I would personally consider the following details to be relevant. Because the Artix 7 FPGA only has one TAP controller to facilitate a JTAG connection, you'll only be able to configure/use the ILA on the board through one connection at a time; either this 6-pin JTAG on J8 or through the microUSB port on J10. There is no integrated UART/serial terminal connection on J8 as the FTDI USB/JTAG solution is not connected to this port. You might be able to get some serial data through BSCAN primitives through the Xilinx software suite in SDK/Vitis, but Digilent doesn't have support for this particular setup. You'll need an external JTAG programmer of some kind to connect to J8 in order to be able to configure the board as the on-board FTDI solution is not connected to this port. The board will need some sort of external power supply as you cannot power the board through this connection. If you're using port as an alternate way to configure the device with an existing bitstream without needing to install Vivado (perhaps for out of the office configuration), make sure your solution facilitates all of the configuration styles you need. Digilent's Adept software for example does not have support for configuring the flash memory. (In theory, you could configure the flash via Adept with a SVF file, but I was unsuccessful programming the flash with an SVF file directly from Vivado. Your mileage may vary) There might be more things, but that's what I can think of at the moment. Thanks, JColvin

Hi @tim.schumacher, Digilent does not have such a cable, no. This Forum thread discussed some alternate solutions that might meet your needs though: Thanks, JColvin

Hi @vinod, My understanding is that unless you are able to reduce your image size (Xilinx has some information on this here: https://docs.xilinx.com/r/en-US/ug1144-petalinux-tools-reference-guide/Managing-Image-Size), then the option is going to be to have the Zybo Z7-10 instead boot from an SD card. Xilinx has some information on how to do that here: https://docs.xilinx.com/r/en-US/ug1144-petalinux-tools-reference-guide/Booting-PetaLinux-Image-on-Hardware-with-an-SD-Card. Once you have the needed images, you can put them on the SD card, insert it into the Zybo Z7-10, set jumper JP5 to SD instead of QSPI, and then power it on and connect it to a serial terminal of your choice. Regarding your question of putting the BOOT.BIN in QSPI flash and the image.ub on the SD card, I do not think this is readily possible to do with how the bootloader finds the other files (or at least I am not able to find any information on how this partial boot from multiple locations might be done). Thanks, JColvin

Hi @john2022, I have sent you a PM. Thanks, JColvin

Hi @John J, I've reached out to an engineer with a bit more insight into the Genesys ZU; however they are out of the office until sometime next week. Thanks, JColvin

Hi @Wade, I do not think you will run into any issues using just the USB Type C connection, particularly if the host computer end is also a Type C connection. Or at least I have not run into any power issues; you would be realistically more limited by the current output of the Analog Output channels as they are only able to supply up to 30 mA for distortion free generation (40 mA before hardware cutoff); https://digilent.com/reference/test-and-measurement/analog-discovery-3/specifications#arbitrary_waveform_generator_wavegen. Let me know if you have any questions. Thanks, JColvin

Hi @AdityaSeelam, Based on what you have posted I have the following questions and suggestions. Does the module you are using have integrated pullup resistors for the SDA and SCL I2C lines? If not, you will want to add that parameter (PULLUP TRUE) to the corresponding .xdc lines. It looks like you are wanting to use Pmod JE pin 1 and pin 2 as the I2C pins. Since you appear to be wanting to use the I2C controller within the Zynq processor as the driver of the I2C bus, you will need to do the following things: Open up your Zynq Processing Block and go to the MIO configuration tab; check the box for either 'I2C 0' or 'I2C 1' (doesn't matter which one) and have the dropdown selection be EMIO (extended MIO). On the newly available I2C connection on the Zynq Processor within the Block Diagram, right click on it and choose to make this connection External. Screenshots illustrating this step and the one directly above are available in this post here: https://forum.digilent.com/topic/24428-zybo-z720-audio-codec-i2c-pins/#comment-72313. (alternatively, instead of EMIO for I2C, you can use MIO and pick one of the Pmod JF pins as the connection points, such as MIO 12 and 13 for I2C1. Page 10 of the schematic shows the MIO connections to Pmod JF on Bank 500, https://files.digilent.com/resources/programmable-logic/zybo-z7/zybo-z7-d1-sch.pdf) Adjust the Constraint pin names match whatever you have named the external I2C EMIO connection. When using the default name, this will probably be something like IIC_0_0scl_io and IIC_0_0_sda_io. If these aren't the correct names, Vivado will complain at some point during the bitstream generation that the pins in question are not constrained and you will be able to check the exact names within the wrapper. You would then control the pins through something like the I2C-PS controller: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841822/I2C-PS+standalone+driver. Let me know if you have any questions. Thanks, JColvin

Hi @Yatharth Gupta, DDR memory on Zynq based boards are connected directly to the PS, so you do not use a mig.prj like you would for a non-Zynq 7-series board. Presuming you have the Digilent Board Files installed (either via this method, https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files, or by installing them via the Xilinx Board Store when initially choosing a part upon creating a project), after you add the Zynq processor to your block design, run block automation and leave the Apply Board Preset checked, and the DDR memory will be connected for you; https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_a_processor_to_a_block_design. Let me know if you have any questions or if I am misunderstood what you are wanting to do. Thanks, JColvin

Hi @Jana Saleh, The Digital Discovery is not able to use an external clock but does have a Sync mode which may be helpful for you. Check out these two threads for more information: Let me know if you have any questions. Thanks, JColvin

Hi @Tparng, Since you didn't directly clarify this, do you have the Vivado Hardware Manager open at the same time and connected to the Zedboard at the same time while trying to configure it through djtgcfg? This would be a point of failure if the JTAG access was otherwise already claimed. Otherwise the Adept developer clarified to me that Adept should be able to program the PL of the Zynq 7020, but this has not been thoroughly tested. Adept is not able to configure the PS (or flash memory in general for non-Zynq devices). Let me know if you have any questions. Thanks, JColvin

Hi @janpi, I'm not Attila of course, but this is what I get for Channel 3 with no probe or shorting: The offset appears to be different than yours, but is otherwise of a similar magnitude. Thanks, JColvin