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JColvin

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Everything posted by JColvin

  1. Hi @ez4game, I have sent you a PM on how to restore the SMT1 present on the VC707. Thanks, JColvin
  2. Hi @gnarco, I have sent you a PM. Thanks, JColvin
  3. Hi @zzz, I'm sad to hear the customer experience is not what you wanted. The Forum here is where the Digilent support engineers, such as myself, are able to answer questions in such a way so that other customers with similar queries can also benefit from the answer. Cancelling the order would be done through your Store account, or there's likely a way on the order confirmation email to send a message to the order support team with your order number already associated with the message. Otherwise you can fill out the form on here: https://digilent.com/shop/sales-and-order-support/. In terms of deleting personal information, there is a form for it available in our Legal & Privacy page, https://digilent.com/shop/legal-privacy/. Ctrl+F for "Data Request Form" will jump to the form you're looking for. I doubt you're inclined at this point to let me know which particular aspect you feel is unfair, but feel free to post back or private message me with details. I'm not on the compliance team or anything like that, but my gut feeling is that particular line items are more likely to be considered than blanket statements. Thanks, JColvin
  4. Hi @ctkilian, I asked another engineer who was more familiar with the Pmod ToF about this and they reminded me that the embedded ISL29501 chip needs to be calibrated before any data is taken (which isn't very well explained in the datasheet that I linked earlier). Digilent has some additional information on this Chip Initialization step within the documentation for the FPGA Hierarchical Block Library, https://digilent.com/reference/pmod/pmodtof/libraryuserguide#isl29501_-_time_of_flight_tof_integrated_circuit. Renesas also has information on this initialization and a mention that a set of registers need to be initialized before you can calibrate the module so you can properly take measurements in their Application Note here: https://www.renesas.com/us/en/document/apn/an1724-isl29501-firmware-routines. After those registers are set up, you can then load the Digilent provided factory calibration that is stored in the EEPROM into the ISL29501. The reading of the EEPROM, described a bit more in the Library User Guide I linked, is a bit more involved, with several functions in the library Digilent facilitated to read the values and write them to the volatile ISL29501. The PmodToF_RestoreAllCalibsFromEPROM_Factory function starting on line 472 in the PmodToF C source file, https://github.com/Digilent/vivado-library/blob/hierarchies/hierarchies/PmodToF/sdk_sources/PmodToF/PmodToF.c, will probably be the most helpful to you in terms of determining all of the needed steps to get the factory calibration loaded. Thanks, JColvin
  5. Hi @rbuisson_tdk, I have sent you a PM. Thanks, JColvin
  6. Hi @Abhijan, The first thing I would be checking with the 1:10 ratio would be the attenuation setting on the BNC probe. It's also worth ensuring that your two devices share the same ground connection. Let me know if you my guess is not accurate to your situation. Thanks, JColvin
  7. Hi @jfm, When you connect to the micro USB port to your laptop, is the jumper that is next to the barrel jack set to the USB setting side (as opposed to the external power side)? The power good LED next to that same jumper should light up. If the jumper settings are correct and the LED doesn't light up, I would first recommend trying a different USB cable (especially if when you connect to your computer you are not able to find evidence of the connection in the Device Manager). It is also worth noting that the Cora Z7 does not have any flash memory, so there is not an out-of-box demo that will load on power-up as there is not static memory to load from (presuming I remember correctly that the Cora Z7 does not ship with an SD card). If the power LED is lighting up, you can test the Cora Z7's functionality though the Example Projects available on its Resource Center: https://digilent.com/reference/programmable-logic/cora-z7/start#example_projects. Let me know if you have any questions. Thanks, JColvin
  8. Hi @Ahmed Bahaa, When you initially added the CAN to the Logic Analyzer instrument, what settings did you use? Additionally, what voltage is your CAN network operating at and could you attach a picture of your setup? Thanks, JColvin
  9. Hi @Airmanblu, The SPI protocol, even though there is only a singular device on this bus, dictates that the chip select line is pulled low during every transaction because there is not an addressing scheme like I2C (https://www.ni.com/en/shop/labview/understanding-the-spi-bus-with-ni-labview.html). Because there is no pulldown resistor on the SS line of the Pmod CLS (you can verify this for yourself on the schematic, https://digilent.com/reference/_media/reference/pmod/pmodcls/pmodcls_sch.pdf) you'll need the jumper on JP1 set to short the middle pin to the SS side, as well as needing to connect a wire from the NI myRIO to pin 1 header J1. Let me know if you have any questions. Thanks, JColvin
  10. Hi @tom.des, I have sent you a PM with some instructions. Thanks, JColvin
  11. Hi @MicNZh, I have sent you a PM. Thanks, JColvin
  12. Hi @boris_skier, It's unlikely to return since Digilent wasn't the manufacturer of this particular product (it was NKCelectronics), but it appears their website is no longer readily available. I will mention that there is interest in creating such a product, though to be honest for one-off projects it would probably be more effective for users to create own shield in exactly the way they desire based off of the dimensions taken from the 3D model of the Arty A7, https://digilent.com/reference/programmable-logic/arty-a7/start#additional_resources. Thanks, JColvin
  13. Hi @Airmanblu, I don't have a Pmod CLS with me at my home office to test this, but you are correct that MO0 should be the only jumper that needs to be loaded with regards to JP2. You'll also need to set JP1 to the SS side so that any Chip Select signaling gets routed to the correct pin on the embedded microcontroller. The supplied 3.3 V from the myRIO should be fine. Thanks, JColvin
  14. Hi @BigBob, I moved your thread to where the WaveForms developer will be able to more easily see your suggestions and feedback. I'm not the developer, but do have a couple of clarification questions. Could you explain a bit more of what you mean by "Live-Data"? Are you referring to effectively watching a .csv file being created "live", or something else? And I guess more relevantly, what feature are you imaging this other software receiving the analog/digital data doing that WaveForms does not currently support? The software-trigger I am imagining to be somewhat controversial as it is inherently slower than the trigger bus that is implemented in hardware, so by the time a Math trigger is detected, the hardware condition you want to catch could have already passed. What sort of timing resolution would you be envisioning with this? Thanks, JColvin
  15. Hi @RakeenJ, I apologize for the delay. I was out of office all last week. It appears you have overwritten the EEPROM like many other users: I have sent you a PM with some instructions. Thanks, JColvin
  16. Hi @jowell88, I apologize for the delay regarding on questions 2 and 3; this is the clarification that I have received. C177 and C178 are both present because VrefCA and VrefDQ as per the Micron datasheet (https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_1_35v_ddr3l.pdf) on Table 22 expect to have voltages of Vdd/2. DDR3_Vref sources this from a voltage divider (middle of page 10 of the Zybo Z7 schematic), and then the combination of C177 & C179 and C178 and C180 provide further stabilization of this voltage as required by Table 21 and Table 22 of the Micron datasheet. Addtionally, VrefCA and VrefDQ should track any variations on Vcc1V35. So the two equal-value capacitor pairs will represent relatively small impedances for short-term variations from Vcc1V35, effectively forming voltage dividers that cause short-term variations on Vcc1V35 to be tracked by both Vref inputs. You are correct that the EXTEST operation will not work on the Zybo Z7 as per the note Table 5-3 in UG933 and the corresponding answer record (https://support.xilinx.com/s/article/57930?language=en_US). There is no way to temporarily change the bank voltage on MIO1/Bank 501 from 1.8 V to any other value on the Zybo Z7. Let me know if you have any questions. Thanks, JColvin
  17. Hi @jcbdev, I have sent you a PM. Thanks, JColvin
  18. Hi @YongBin, Digilent doesn't have anything designed for the ZC706 from Xilinx, but there are a couple of example projects for the FMC Pcam Adapter, https://digilent.com/reference/add-ons/fmc-pcam-adapter/start#example_projects, that use the Zedboard (a Zynq 7020 based board) that might be feasible to port to the ZC706, though I haven't looked into how different the ZC706 is. Each page for the example projects has a link to their respective GitHub repositories with the source code. Thanks, JColvin
  19. Hi @ctkilian, The module not drawing any current (I'm not sure how you are measuring this) is not necessarily a red flag since as per the datasheet of the onboard IC, https://www.renesas.com/eu/en/document/dst/isl29501-datasheet, it is only drawing at most 2.5 uA during sleep mode which the module is put into after a STOP condition after a Read command or after a write command has completed (page 13). By default, the module is primed to be going in free running mode (register 0x13 bit zero) but it requires a trigger (pulling the sample start, pin 2, from high to low) before this occurs (page 16). As for addressing the module, sending 0xAE is correct if you want to do a write command (since write would put that last bit low); the module should respond with an ACK after receiving the chip address, though if you send a Stop condition from the host prior the completion of the data byte and the corresponding ACK from the Pmod, the Pmod ToF (or more specifically, the ISL29501) will reset itself back to sleep/standby mode. Let me know if you have any questions. Thanks, JColvin
  20. Hi @yunzhenghan, I haven't used Petalinux, but it should already be pulled in for you when you import the .xsa file from Vivado. The basic flow for the OLED driver is mentioned in this thread here: Let me know if you have any questions. Thanks, JColvin
  21. Hi @RyanW, My understanding is that the firmware on the Platform MCU which controls the state of VADJ will by default/on power up will have the VADJ rail disabled until it parses the EEPROM memories of the attached device to determine the correct VADJ to use. An LED fault indicator will be shown and the VADJ rails will remain disabled if no compatible VADJ voltage is found (such as if an FMC mezzanine module and SYZYGY pod have mismatched values, or request a VADJ that the Genesys ZU is not able to supply). I have asked another engineer more familiar with the Genesys ZU what additional actions you can take to help ensure the correct voltage upon power up. Thanks, JColvin
  22. Hi @Zhang416, Thank you for the information. From my understanding, even if you were on the high gain setting for the Zmod Scope (+/-1 V input range) when applying the 2 V square wave (presuming the Eclypse Z7 & Zmod were sharing a common ground with whatever device was generating the 2 V signal), the Eclypse Z7 should not be damaged by this, or at least not the 1.8 V rail. If you purchased the board directly from Digilent and wish to exchange it, please send me a private message with the following information: - Order Number - Purchase date - Board Serial number (barcode sticker on the underside of the board starting with "D") - preferred email contact so I can get the information to our Sales team who will then follow up with you to confirm any additional information from you, such as shipping address, that I don't have access to. If you instead purchased the board from a distributor (Farnell, Amazon, etc) you will need to contact that distributor directly for their own RMA process. The distributor will then contact Digilent directly as needed. Feel free to reference this thread as having done troubleshooting with a Digilent engineer. Thanks, JColvin
  23. Hi @Zhang416, In the interest of avoiding confusion or presuming inaccurate information, I'm still going to ask for a more specific set of voltages; a more contained list of the voltages as well as a reference image for their location is in this post: Could you also let me know a bit more what you were doing with the Pmod port? Just using it with some module, using it plus a Zmod, something else? Thanks, JColvin
  24. Hi @aceblen, I'm not certain which version of Vivado you have or which Pmod tutorial you might be using (I'm presuming this one that was made for pre-Vitis era, https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start). I don't know what you mean by opening up an IP core in Vitis, but in terms of getting most Pmod modules working in newer versions of Vivado (I haven't tested any Pmods with 2023.2 with its new underlying IDE), but in general the approach in Vitis is largely the same as SDK. The only major difference is that when adding in the IP core to the Block Diagram in Vivado you'll need to right click on the output of the Pmod IP and choose to make the output external. You'll then create a .xdc file that matches the pin names of those external pins (names of which can be found in the wrapper after you have Vivado validate the Block Design and create the wrapper for it). There is some more detail about this process in this thread: Let me know if you have any questions. Thanks, JColvin
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