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Posts posted by JColvin

  1. Hi @JohnA.,

    The PS_SRST_B is available on the JTAG header on pin 14; there is a reference image showing where it is on the Xilinx JTAG header on the JTAG HS3 reference manual here: https://reference.digilentinc.com/jtag_hs3/refmanual#xilinx_zynq-7000_and_soc_support.

    I think for the jumpers you will need to change MIO2, as per the the Zedboard User Guide (pg 28) the current setting puts it in Independent JTAG mode which as per AR# 47599 from Xilinx the PS on a Zynq chip cannot be accessed through the ARM DAP which is affected by the CES chip versions. Could you try setting this value to be in Cascaded JTAG (settings the signal to ground)?


  2. Hi @JohnA.,

    I don't have ISE available to directly test this (since I'm on Windows 10), but on Vivado and SDK, I was able to to successfully load the .bit file and the application project launched. If I have a second USB cable attached to the PROG port (J17), then I am not able to readily choose to load the application.

    I don't know what tool you are using to load the file via the standard JTAG board, but do you happen to know if the tool you are using as the capability to drive the PS_SRST_B low? Xilinx tools occasionally require the processor core to be reset during debug operations (of which launching on hardware (system debugger)).

    As an additional question, what version of the Zedboard do you have and how are the mode jumpers configured on it (I realize you tried a number of options already, but in the interest of being on the same page.

    I do not think there is a way to load it through the UART USB as it is not connected to the necessary programming lines.



  3. Hi @JohnA.,

    I'm not certain why you need to decouple to two JTAG ports (since the UART port is separated from the programming port or if there is a different reason), but if you use something like the JTAG HS3, you can then use the Digilent Adept software to load the .svf file to the downstream Zynq SoC.

    Let me know if this is not what you are looking for.


  4. Hi @Robert Craven,

    The Pynq Z1 with it's Arduino styled shield connector (more details in the Pynq Reference Manual here) can drive 20 MOSFETs (provided the MOSFETs have a Vgs at 3.3V) since as per the Xilinx Zynq 7020 DC and AC Switch Characteristics datasheet, each pin can provide up to a maximum of 10 mA, with a total of 200 mA per bank. The IO on the shield connector are split between a couple of different banks so ideally you will not run into the current limit for each bank, though you will likely want to double check.

    Let me know if you have any questions about this.


  5. Hi @Michal Hucik,

    Could you provide a picture of your setup so I can see how the board is powered?

    Is the Nexys A7 able to be detected in the Vivado Hardware Manager (or alternatively, the Digilent Adept software)? The other thing I might recommend is trying a different USB cable or USB port since it seems based on the output that Xilinx SDK is able to detect the board (via the jtag_cable_name) but then is not able to properly detect the board afterwards.


  6. Hi @zbd,

    The supported display resolutions are as follows:

    640x480 at 60 Hz
    800x600 at 60 Hz
    1280x720 at 60 Hz
    1280x1024 at 60 Hz
    1600x900 at 60 Hz
    1920x1080 at 60 Hz

    so to answer your question, the specific display resolution of 1920x720 is not supported.

    Let me know if you have any further questions.


  7. Hi @mjacome,

    Digilent doesn't provide Vivado so we don't have direct advice, though with the WebPACK edition of Vivado I do not think you need different accounts to install on different computers since the WebPACK version is license free (as of 2016.4). Aside from asking on Xilinx forums about this for more accurate information, I would recommend looking into the batch installation that is described in the Vivado Release Notes.

    Based on that material it looks like you can generate an authentication token associated with your Xilinx account to make the install go easier that expires after 7 days, though I do not know if it is possible to transfer this token between computers. At the very least though there is a command line method to installing Vivado.


  8. Hi @SaltyMathematician,

    I suppose this is possible to do with enough work and time put into it; . I'm not familiar with all of the requirements for a motherboard diagnostics card; i.e. are you testing the full speed capabilities of each peripheral present on the motherboard (PCIe, memory slots,  USB 3.0, SATA III, etc.) or just testing that signals propogate? There are probably some pre-made IPs from Xilinx that test these peripherals though Digilent does not have any examples regarding this.

    The Basys 3 (which uses a XC7A35T-1CPG236C FPGA) may not be fast enough (you can view it's capabilities in the Artix-7 DC and AC Switching Characteristics datasheet from Xilinx) to perform some of the diagnostic tests. I'm not certain what the end application you are looking for is in this situation, though I might recommend looking into a premade solution unless you are set on creating your own.


  9. Hi @chcollin,

    I think you still might need the Micron flash family based on the Xilinx xilisf documentation and based on the paragraph starting on line 35 on the Xilinx GitHub here; mostly I'm pointing this out since I'm not sure how the flash will react to incorrect commands (it all depends if it cancels the command or does something unexpected). But there is also the chance that my Micron family thought is incorrect.

    I'll look for an equivalent version of the FLASH_DEVICE_ID that you found.


  10. Hi @JHall,

    If you wanted to upload a bootloader to the OpenScope MZ, you would need an ICSP programmer (such as the chipKIT PGM or a picKIT3) to program the .hex file that contains the bootloader in the Firmware section on the right-hand side of the OpenScope MZ Resource Center via JP2 on the OpenScope MZ. There is a guide on how to update the bootloader here.

    It is critical that you only use this .hex file via the ICSP connection; if you attempt to load the unifed .hex file with the bootloader rather than the .hex file that does not contain the bootloader via WaveFormsLive, the OpenScope MZ will not function correctly if you use the wrong one.

    The other thing I will mention is that the Arduino IDE material is for an older firmware (1.296 rather than the current 1.301.0); the only change I can find that happened though is documented here: https://github.com/Digilent/openscope-mz/commit/fac636014a6166db18889101563dcbd761c73ba9, so since the change is only in HTMLPostCmd.cpp, the material should still work over the Digilent Agent via USB, though I'm not certain if it would still work over WiFi.

    Let me know if you have any questions.


  11. Hi @JHall,

    Unfortunately, we do not have a lot of advice with regards to using Arduino IDE with the OpenScope MZ as shown as in these threads here, here, and here.

    However, I tested this on Arduino IDE 1.6.9 and was successfully able to compile the project. Did you close the Arduino IDE after adding the Digilent Core and the OpenScope material? Additionally, I didn't do the git clone of the material; I simply downloaded the .zip file, and extracted/moved the files from within 'openscope-mz-master' to an empty file folder called "OpenScope" in the Arduino libraries folder (again, making sure that the Arduino IDE is either closed during this operation or either restarted after this move has happened). I then opened the OpenScope.ino file from Arduino IDE 1.6.9, and was successfully able to compile the material as is, though not upload since the incorrect bootloader is currently on my board.


  12. Hi @chcollin,

    Re-reading the tutorial, the bootloader that is provided is intended to reader from the SPI flash via the Xilinx In-System Flash library (as opposed to the default provided by SDK that uses parallel NOR Flash) specifically for the flash on the Spartan-6 LX9 MicroBoard.

    Based on Table 5-5 (Spartan-6 FPGA Bitstream Length) in the corresponding User Guide, the default bitstream length is much larger for the LX45 device (11,939,296 bits), corresponding to 1.4574 MB. Looking at the flash used on the Atlys (a N25Q128 Numonyx chip which has 64 KByte sectors), this would use the first 23 sectors, leaving 233 sectors (~14,900 KBytes) for the application. It is also possible to compress the bitstream to have it use less resources, though I don't know how much it would get compressed. Extrapolating from the Avnet tutorial, the offset to choose in the blconfig.h file (create boot loader application, step 9) should be 0x170000.

    With regards to the flash family, I think you would want to choose the 5th one (Spansion) based on the Xilinx documentation for xilisf, since that Spansion option also apparently counts for Micron (and I understand the Numonyx chips are now owned by Micron), though I am uncertain about this since the tutorial I linked you to states that Micron devices have the same control set as STM (option 3).

    I'm not certain on the XPAR_SPI_FLASH_DEVICE_ID bit; everything that I have found leaves this value unchanged. I'll keep looking and let you know if I find something.


  13. Hi @MatthewNevels,

    I have attached a .zip file containing the .step file and the dimensional drawing of the DMM Shield. I will note they are not the fanciest drawings (for example, it doesn't include the pins that are used to load the shield onto the host board), but should have the other relevant dimensions that you would need. Let me know if you need some particular dimensions measured and I can measure those with calipers for you.



  14. Hi @MatthewNevels,

    The SPI material works because the SPI protocol is bit-banged rather than using the hardware SPI and have the bit-banged SPI pins defined in gpio.h as 11, 12, and 13, which is available in Arduino DMM Shield Library on our GitHub: https://github.com/Digilent/Arduino-DMMShield-Library.

    With regards to your two requests, I don't have an Arduino pinout available as of yet, but I did adjust the 'top row' and 'bottom row' labeling in the Reference Manual here: https://reference.digilentinc.com/reference/add-ons/dmm-shield/reference-manual#appendixpinout_tables, to inner and outer row to make it less ambiguous. Let me know if there is an alternate phrase that you feel would be better.

    I have asked another engineer if we can get a 3D model or mechanical file for the DMM Shield.


  15. Hi @jonpaolo02,

    I was able to get the WiFi IP working successfully on the Zedboard with Vivado and Vitis 2019.2 This is what I did to get to working :

    1. Build Block Design as normal in Vivado 2019.2 (i.e., I followed the Getting Started with Pmod IPs, and used the latest Vivado library zip download from the Digilent GitHub).
    2. Create the HDL wrapper for the block design, generate the bitstream, and export the hardware including the bitstream via the File->Export->Export Hardware option. This will create a .xsa file that Vitis uses.
    3. Under the Tools option, choose Launch Vitis.
    4. After Vitis has successfully launched, choose the "Create Platform Project" under the Project header in the middle of the GUI. Choose a name for it and click Next.
    5. Choose "Create from hardware specification (XSA)", click Next, and then browse for the XSA file that Vivado created in step 2. Keep the operating system as standalone and processor as ps7_cortexa9_0. You can choose to keep the Generate boot components checked or unchecked, though I did not test the boot components on my project in the in the interest of having less variables to worry about.
    6. This will create the create the platform in Vitis. I right-clicked on the platform project and chose "Clean Project" followed by "Build Project"; I'm not certain if those steps are a required, though it doesn't hurt.
    7. I then clicked on File->New->Application Project. I named the project and clicked Next. Under the "Select a platform from repository" tab, I selected the platform I named earlier (in this case, "Zed-WiFiSD-19-2") and clicked Next. I changed the language used to C++ and maintained the standalone OS on the ps7_cortexa9_0 CPU and clicked Next. I choose Empty Application (since that was the only option) and choose Finish.
    8. From there, I followed the same procedure used in SDK 2019.1; i.e., I copied the HTTPServer stored in the [platform_name]->hw->drivers->PmodWIFIF_v1_0->examples folder to the src folder in the application project created in Step 7, and made the changes to deWebIOServerSrc.cpp and HTTPServerConfig.h.
    9. At this point, the only thing missing is the .elf file in the application project so it can be successfully launched. I was able to get it generated within the (currently missing) Binaries folder by right clicking on the application project (I choose the one with the "_system" in it's name) and choosing "Clean Project" followed by "Build Project" once the former has finished. This generated the .elf file.
    10. There was an error listed in the project that states the .elf for the FSBL was not found, but since the Generate Boot Components option was left unchecked, I ignored this error. After turning on the Zedboard and connecting to it via a serial terminal, I then clicked on the Xilinx tab, chose "Program FPGA", and then right-clicked on the application project and choose Run As->Launch on Hardware.

    Please let me know if you have any questions about this.


    design_1_wrapper.xsa vitis_export_archive.ide.zip