JColvin

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Posts posted by JColvin

  1. Hi @Eric888,

    The Xilinx Platform Cable USB II is a 2x7 connector rather than the 1x6 header that is present on the Nexys Video. So you would need an adapter that accounts for the pin orientation changes if you wanted to use the Platform Cable, though I haven't seen such an adapter that also accounts for the difference in pin layout.

    If you are just wanting to connect to the board to load designs, you can use a micro USB cable (that isn't charging only) on header J12. Serial/UART communications are available through a second micro USB connector on J13.

    Let me know if you have any questions.

    Thanks,
    JColvin

  2. Hi @Troglobyte,

    It looks like your Block design does not have anything in it, though it seems you figured that out from based on your other forum thread:

    For future reference though, Digilent has a guide on creating block designs for Vivado which includes both Microblaze and Zynq based designs available here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi.

    Thanks,
    JColvin

  3. Hi @VerticalFarmingStudent,

    Digilent does not have any further information about this demo. The material (or lackthereof) was created by a former intern about a year back which to my understanding was porting some of the Xilinx AI materials to the Zybo Z7, but unfortunately they did not create any documentation associated this demo, so we've removed this under construction page from our Wiki to prevent further confusion.

    I don't think Xilinx has a lot of up to date details on SDSoC as they have moved away from that towards Vitis AI instead, https://www.xilinx.com/products/design-tools/vitis/vitis-ai.htm, though as @zygot mentioned, Xilinx's offerings may not be a low cost path for this type of application. I haven't looked a lot into this, so there may be a lot more support available through Xilinx than am I aware of.

    Thanks,
    JColvin

  4. Hi @zygot,

    To confirm, since I can't quite tell from the way you phrased it, the provided trace lengths did detail the rx_ctl and rxd traces you needed, correct? As far as I can tell from the RTL8211E datasheet, the RXCTL pin is on the same pin location as RXDV (for a different pin package) which both have the pin name of PHY_AD2, and the trace length document seems to list the RXDV_X trace lengths.

    Thanks,
    JColvin

  5. Hi @dmeads_10,

    I asked about this and was provided the attached datasheet; I was told though that you might have some trouble being able to source this, or at least I wasn't personally able to find the any sort of exactly matching part on the manufacturers website (or at least the list of heatsinks for Xilinx chipsets doesn't list a SFVC784 package, http://www.malico.com.tw/index.php?option=com_content&view=article&id=416&Itemid=148&lang=en) though the datasheet does provide all of the dimensions of the part.

    The thermal paste should be generic as far as I understand though.

    Let me know if you have any questions.

    Thanks,
    JColvin

    HBF23031-16_1.5Y+T710 A1.pdf

  6. Hi @meakerb,

    I've always pronounced it Zee-bo because it's a Zynq board, but there isn't any official confirmation on that. I asked our Marketing Manager about it and he pronounces it both ways, so that's a thing.

    I guess the tl;dr is pronounce it however you like, but there's also an official poll for the pronunciation now:

    Thanks,
    JColvin

  7. Hi @zygot,

    The Rev F schematics are available on the 1G CML Resource Center (https://reference.digilentinc.com/programmable-logic/netfpga-1g-cml/start). I asked about the trace lengths and got some details that I have attached. I don't know exactly which signals you were looking for in particular.

    In terms of support, what I have been told (at least this was the case last year) is that Digilent will do some hardware error support, but if you are not able to get help from the NetFPGA mailing list (links for it are available here: https://netfpga.org/site/#/systems/2netfpga-1g-cml/support/) then you should be able to get support including software support from CML, via the email support (at) cmlab (dot) biz.

    Let me know if you have any questions.

    Thanks,
    JColvin

    NetFPGA-CML RXD trace lengths.txt

  8. Hi @tsbw83,

    I was able to simply create a new folder called board_files in the Xilinx\Vivado\2021.1\data\boards folder and then add in the Digilent board files. Freshly opening Vivado after that let me see the Digilent board files as expected. I'll request that the associated Digilent board file installation tutorial is updated to reflect this.

    Thanks,
    JColvin

  9. Hi @tsbw83,

    My understanding is that all versions of the Vivado software are compatible with both variants of the Zybo Z7.

    If it makes a difference to you though, not all of the demo materials that Digilent has available for the Zybo Z7, https://reference.digilentinc.com/programmable-logic/zybo-z7/start#example_projects, have been updated and confirmed to be working with every version of Vivado. I believe the latest version that the demo materials were updated for was 2020.1 based on our GitHub releases for the projects: https://github.com/Digilent/Zybo-Z7/releases.

    Let me know if you have any questions.

    Thanks,
    JColvin

  10. Hi @VerticalFarmingStudent,

    Yes and no.

    Is it possible to do? Yes.
    Is there an already created design that I can point you towards that you can run with no modifications to the project? No, not that I am aware of; almost all Zynq and camera based designs that I have seen are done in an Linux OS; which you can set up on a Windows OS through either dual booting or a virtual machine.

    I did find some more links regarding using a Zynq based platform and computer vision which may be of interest to you though: Link1, Link2, Link3.

    Thanks,
    JColvin

  11. Hi @Keaton,

    I apologize for the delay.

    I haven't gone through this library specifically, but unfortunately most of the libraries that I've looked at online have some sort of error in their calculations or register manipulations. The Pmod IA has also been retired for quite some time so there isn't a lot of available support for. The best I can do is direct you to this thread: https://forum.digilentinc.com/topic/4375-pmodia-returning-incoherent-impedance-values/?sortby=date.

    I'm sorry I couldn't be of a lot more help.

    Thanks,
    JColvin

  12. Hi @Victor C,

    The Pmod IA was retired some time ago so there isn't a lot of support around it available. There was also some (in my opinion) inherent user friendliness issues with the embedded AD5933 chip and I was never able to find a C based library that correctly manipulated the registers. The best material I can point you towards is this thread: https://forum.digilentinc.com/topic/4375-pmodia-returning-incoherent-impedance-values/?sortby=date.

    I'm sorry I couldn't be of much more help.

    Thanks,
    JColvin