JColvin

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Everything posted by JColvin

  1. Hi @[email protected], Here is the correct link to the release page: https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO/releases. The link in step 1 of the readme is being corrected as I'm typing. You will need to generate the bitstream (and the synthesis will be out of date) as per step 4 before exporting the project to SDK. After the bitstream is generated (for the 2018.2 project, I don't think you need to generate a bitstream for the 2019.1 release), did you then import the sources into the SDK project? Thanks, JColvin
  2. Hi @jrochette, I've sent you a message with some instructions. Thanks, JColvin
  3. Hi @armandomisista, I've sent you a PM with some instructions, though I am not certain if they will work for your situation. Thanks, JColvin
  4. Hi @DaveS, I'm glad a different cable worked, though as to why this is the case (or why different boards work with different cables) I do not know. I believe (I haven't gotten confirmation) that Digilent changed out the micro B USB cable that we sell to one that was tested to work consistently, though I have personally been using the same cable that was found to problematic for the last 5 years without any issues. So I'm glad you were able to find an easy solution. Thanks, JColvin
  5. Hi @[email protected], The 4 camera connection is the same GitHub link that is provided in this specific post here: https://forum.digilentinc.com/topic/19768-pcam-5c-with-zedboard/?do=findComment&comment=54467. The dual camera GitHub link is available here: https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-Dual-Camera. The warning and 2 infos/tasks I presume you have (the warning and 2 infos I have on my 4 camera FMC project are: warning: this statement may fall through [-Wimplicit-fallthrough=] ZedBoard_FMC_Pcam_Adapter_DEMO_bsp line 246 C/C++ Problem Info 1: #pragma message: For the sleep routines, Global timer is being used xtime_l.h /ZedBoard_FMC_Pcam_Adapter_DEMO_bsp/ps7_cortexa9_0/include line 89 C/C++ Problem Info 2: here ZedBoard_FMC_Pcam_Adapter_DEMO_bsp line 247 C/C++ Problem) can likely be ignored as they are informing you of details that are directly built into the Xilinx material; i.e. the first info message is simply repeating line 89 in xtime_l.h verbatim. I am a little confused on your tasks. Each of the ports on the FMC Pcam adapter already use the same power enable, PWUP. Additionally, the purpose of the demo is to facilitate the MIPI and CSI-2 communication. The D-PHY was already taken care in the layout of the board. Thanks, JColvin
  6. Hi @mukunda, I don't know what moisture sensor you are referring to, but one potentially easier route would be to see if a Digilent Pmod (which does have an IP core available in the Digilent Vivado library, https://github.com/Digilent/vivado-library/tree/master/ip/Pmods) and then modify the SDK material to properly analyze the data for the moisture sensor. Thanks, JColvin
  7. Hi @NaN, Digilent does not provide the Xilinx software, so we are not able to offer discounts on their licensing. I took a look at the licensing question that is referenced in the FAQ of the NefFPGA-1G Wiki (as they created and maintain all of the software and designs for the NetFPGA-1G-CML) and learned that if your university does not have a pre-existing agreement with the Xilinx University Program, you may need to instead use an evaluation version from Xilinx; there are further details about this here: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Licensing. One thing I did notice though on their FAQ is that the designs they have are for ISE 14.6 and as far as I could tell the NetFPGA group does not have existing material for Vivado Design Suite with regards to the NetFPGA-1G-CML. Thanks, JColvin
  8. Hi @Hidehisa Nishigaki, All Digilent products are compliant with the RoHS Recast as amended by EU directive 2015/863. I have attached our RoHS Certificate of Compliance for your convenience. I confirmed our Engineering Services Manager that JTAG HS3's purchased in 2017 are also compliant with EU 2015/863. Thank you, JColvin Digilent RoHS CoC.pdf
  9. Hi @Samsonnn, I have sent you a PM. Thanks, JColvin
  10. Hi @Raghunathan, Could you attach a picture of your settings? I was unable to replicate the situation regarding the peak to peak voltage (my screenshot is using 50 Hz, but 60 Hz did the same as well). With regards to the square wave appearing curved, I was only able to see this when I zoomed in so that the time base was at 2 uS/division or less but at that point you are just viewing the output settling time of the requested change which should be about 580 nS as noted on slide 91 on the detailed Microchip Masters Presentation. Thanks, JColvin
  11. Hi @perdue, My understanding is that the Adept tools are not configured to detect the on-board Ultrascale+ board as it is not built into the Adept system. You would need to use the Xilinx hardware manager to program and otherwise interact with the VCU118. Thank you, JColvin
  12. Hi @dumbguy, None of these signals in your workspace seem to indicate a SPI protocol. DIN0 and DIN3 seem to be inverse polarity of each other, DIN1 and DIN2 seem to pulse about 8 uSec apart from each other with 16 pulses between the synchronous pulses between DIN0 and DIN3. It also generally (with exception to the 7th pulse on DIO8 and the entirety of DIO11) seems to follow that on every falling edge causes a change on a higher order clock; i.e. every falling edge on DIO8 corresponds with a change on DIO9, and every falling edge on DIO9 corresponds with a change on DIO10. The rapid pulses on DIN1 and DIN2 occur after transitions on DIO8-DIO11 so I do not think they are clocking those longer pulses. I am not certain what protocol represented in general might be though DIN8-DIN10 (aside from the odd 7th pulse on DIO8) is reminiscent of a decimal counter. Either way, I agree with you that there is not any line indicative of being MOSI or MISO or any data line. I would probably ground the black wire to help prevent any spurious issues, though I am not seeing any evidence of problems of cross talk in your attached workspace. Thanks, JColvin
  13. Hi @Glenn Kasten, I don't know why the solutions are provided in a .rar format; as far as I am aware, everything else on the Digilent website (Wiki site and Github included) that is in some sort of packaged format uses the .zip format. I suspect the solutions are done this way because that is how the solutions were provided to us, but I will ask about getting it changed to a more user accessible version. Thank you for pointing this out. Thanks, JColvin
  14. Hi @zliu, I'm not certain what the issue might be. What I will recommend would be to start an RMA. I have sent you a PM with some details that our sales team would need. Thanks, JColvin
  15. Hi @PortAxe, Digilent doesn't have any specific material for the Pmod OLED for the Raspberry Pi. There is a Pmod HAT adapter available that does have some Pmod software support from DesignSpark and RS Components, which does have a library example for the Pmod OLEDrgb. The main SPI pins (including the two chip select pins) are present on GPIO 7, 8, 9, 10, and 11 on the 40 pin Raspberry Pi header. Thanks, JColvin
  16. Hi @alediben, I heard back from the other engineer. They said that since you are considering the SMT2 rather than the SMT3 VBUS does not need to be connected to the module. However, they mentioned that the USB 2.0 specification has an inrush current requirement and as a result, an associated minimum bus capactiance for a usb device and recommended placing a 1.0uF or 2.2uF (10 volt or higher rated) ceramic capacitor between VBUS and GND near the connector, even if you don't intend to draw power. Thanks, JColvin
  17. Hi @zliu, Digilent does not have a tech support phone line, primary because many of the topics that need troubleshooting are ill-suited for an audio based discussion. Since you have not explicitly said so, have you tried a different cable? My understanding is that even if the EEPROM to go with the FTDI solution on the Digilent boards is corrupted in some way, Windows will still recognize that the boards are connected to the computer, albeit as an unknown device. Since nothing is being detected in the Windows device manager (I can't tell if there is anything in your device manager that has an error flag next to it). Thanks, JColvin
  18. Hi @zliu, Have you gotten to try other USB cables? What version of the FTDI driver do you have installed; the latest version (2.12.28) is available on the FTDI website here: https://www.ftdichip.com/Drivers/D2XX.htm. Thanks, JColvin
  19. Hi @wchao_iris, You will likely need a higher voltage for the Pmod I2S2; the Analog to Digital converter chip (CS5343) has a minimum recommended operating voltage of 3.1V, so it will likely not operate correctly when you are trying to debug/listen to incoming analog signals. Is the SCLK clock you listed supposed to be 6.144 MHz? Since I suspect it is not over 6 GHz. Thanks, JColvin
  20. Hi @alediben, I have asked another engineer about this. Thanks, JColvin
  21. Hi @zliu, If you have tried different boards, then I agree that it is not board specific. Could you attach a picture of how you have the board setup while plugged in in case I can spot something weird? And has the board ever worked for you? What do you see in the Windows Device Manager? Normally the Arty board (both S7 and A7) will show up as a "USB Serial Converter" (maybe with an A or B at the end of it) under the Universal Serial Bus Controllers section. Additionally, do the boards themselves power on? One thing to try if you haven't already would be to try a different USB cable (since some USB cables that come with phones are only designed for charging rather than also data) and potentially a different USB port. Thanks, JColvin
  22. JColvin

    EMCCLK for QSPI

    Hi @Sean Kelly, I don't think there is anything like that directly available for the Zynq, or at least I am not able to find anything like EMCCLK in the Zynq Packaging and Pinout Guide (UG865) whereas it is available in UG475 for the non-Zynq 7-series boards. Thanks, JColvin
  23. Hi @Leo_W, I have moved your question to a more appropriate section of the Forum where the engineer most familiar with the Analog Discovery Studio will be able to see and respond to your question. Thanks, JColvin
  24. Hi @HKPhysicist, I apologize for the delay; I thought I had already responded. 1. As it currently stands, there are not any digital protocols that are supported 2. It currently only detects rising and falling edges of a digital signal 3. I am not aware of any sigrok support for the OpenScope MZ Thank you, JColvin