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Everything posted by JColvin

  1. JColvin


    Hi @Ely4, I believe you can use some sort of list command such as some of the ones listed in the RN4871 User Guide, though I will look into this some more. Thanks, JColvin
  2. Hi @emma9513, If that is the case, I would suspect that during the original installation of Vivado that the Zynq chips were not added in. You can add them in by going to the Help tab in Vivado and then selecting "Add Design Tools or Devices". You'll then be asked to log in to your Xilinx account, whereupon afterwards you'll be able to select the Zynq-7000 chips under SoCs in the Devices category. After adding those in and restarting Vivado, you should be able to see those chips and the Cora show up in the board selection screen. Let me know if you have any questions. Thank you, JColvin
  3. Hi @sgrobler and @benl, I was informed today that a conversion process of converting a dlog file into csv is now tested and working for OpenLogger and OpenScope MZ and is documented here: https://reference.digilentinc.com/reference/software/waveforms-live/how-to-convert-dlog. If you have any questions on this, I will try to answer them, but may end up deferring to @AndrewHolzer for the technical side of things. Thanks, JColvin
  4. Hi @mehdi, How did the EEPROM get erased? And you are using the JTAG HS2 with a Xilinx device of some kind? Are you not able to see the JTAG HS2 in Digilent's Adept program? Thanks, JColvin
  5. Hi @mustafasei, I reached out to another engineer about this, but unfortunately they did not have any additional advice for what could be attempted. Thanks, JColvin
  6. Hi @GeorgeMina, Yes, you may attach one Pmod to the top row of the 2x6 header and the other Pmod to the bottom row of the 2x6 Pmod host port; you will need to use a cable of some kind though since the Pmods won't both physically fit on top of each other, but there is nothing electrically preventing you from doing this. I am not familiar with the Nebula board you mentioned, but you should be able to program it such that each Pmod is controlled separately. I don't know if there are any nuances with this particular board that you would have to consider (such as the Pmod port is only compatible with SPI Pmods). Thanks, JColvin
  7. Hi @makedestroyrepeat, Do you know what resolutions you selected? Based on the Pcam 5C demo, it appears that only the 1080P at 30Hz and the 720p at 60Hz are supported and selecting 1080p at 15Hz will cause problems if used. What size/resolution is your monitor that you have connected? Did you also choose the RAW mode as the Image Format? Additionally, what version of Vivado and Xilinx SDK are you using so I can see if I can replicate this? Thanks, JColvin
  8. Hi @nitin.ingle, I'd recommend taking a look at this thread (in addition to the threads attila already linked) as well as the built-in documentation for the Impedance instrument within WaveForms, typically store on a Windows computer here: C:/Program Files (x86)/Digilent/WaveForms3/doc/index.html. Thanks, JColvin
  9. Hi @spaske, Did you take a look at this tutorial that we have for the Analog Discovery 2 here, https://reference.digilentinc.com/learn/instrumentation/tutorials/ad2-impedance-analyzer/start? Thanks, JColvin
  10. Hi @tekson, Did you follow the tutorial that we have for using our GitHub projects here? Looking at your path name and presuming you didn't change any of the names, it appears that you downloaded the source code from the releases page rather than the .zip file on the top of the assets list for the 2016.4 variant. Thanks, JColvin
  11. Hi @Antonio Fasano, I would recommended taking a look at this thread and this one that works on getting interrupts on a Zynq board as well as this thread for just an Arty A7 with interrupts. Thanks, JColvin
  12. Hi @JXS, I'm not certain what all steps you have attempted, so I would recommend following our tutorial on storing an SDK project from flash here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start. It seems to use the same thing that is referenced in the Xilinx answer you linked, though that answer was for Xilinx SDK 2015.1 which I doubt you are using. Let me know how this goes. Thanks, JColvin
  13. JColvin

    Analog Discovery 2

    Hi @Stas Last, I don't have LabVIEW 2017 so I'm not able to open your VI to see for myself. Additionally, are you using Digilent WaveForms VI set or the AD2 toolkit? My understanding is that the AD2 toolkit VI set does not work with LabVIEW 2017, but I think (again, I don't have LabVIEW 2017) the Digilent WaveForms VI should work. There is a thread here that discusses changing the sample rate and sample taken based off of this tutorial though I was unable to get it to correctly display all of those data points on the front panel. Thanks, JColvin
  14. Hi @Luke Abela, My understanding is that the MIG is crucial for this particular tutorial, otherwise you would have to somehow configure the usage of DDR memory without an IP to handle the intracices for you, which is not a trivial task. My recommendation (I'm not certain if you have already tried it) would be to close this project and Vivado and start with a fresh project. To confirm, you have the Digilent board files installed and are using Vivado 2018.2 on Windows 10? Thanks, JColvin
  15. Hi @FloMai, I have moved your question to a more appropriate section of the forum. There is a thread here (containing some additional threads with further details discussing the same topic) that I would recommend looking through. It is possible to use multiple AD2's on a computer though each require their own instance of Waveforms. The total number will depend on your machine setup and power capability. Because each Analog Discovery 2 needs a separate instance of WaveForms you will not be able to see 32 digital channels on a single GUI screen, though you can have one AD2 trigger it's acquisition based on a different AD2. Thanks, JColvin
  16. Hi @RelativeHardware, I'm not certain what the issue might be; is there a particular reason you are not using microblaze? I did attempt to create what you showed in your block design (though I don't have MATLAB to test this), though my block design ended up looking a bit different than yours; I attached an image of it below.. The messages I received while generating the bitstream was Vivado letting me know that the device_temp_i port was not connected to anything, but the bitstream was able to successfully generate. Thanks, JColvin
  17. JColvin

    Firmware via Android

    Hi @Taras, Unfortunately, we do not have any advice with regards to programming an FPGA from an Android device. Thank you, JColvin
  18. JColvin

    Arty Board with RMII?

    Hi @bkzshabbaz, I don't believe there is anything preventing you from doing this, though I would probably use the MII to RMII IP that Xilinx has available, much like this tutorial does for the Nexys 4 DDR. Naturally, you would need to change the xdc pin to match the ETH_REF_CLK to match the one for whichever Arty board you happen to be using. Let me know if you have any questions about this. Thanks, JColvin
  19. Hi @JXS, The bests solution that I can offer would be to use a different/better quality usb cable; there is a collection of other threads on this particular topic with the Cmod A7 on this thread here: Thanks, JColvin
  20. JColvin


    Hi @Saad, There is a 3D model for the Cmod A7 (likely the 35T variant) on the Cmod A7 Resource Center on the right-hand side under Design Resources. As @xc6lx45 indicated, they will be mechanically identical. Otherwise, we do not provide the Altium files for our products. Thanks, JColvin
  21. Hi @ub3rmike, I have sent you a PM about this. Thanks, JColvin
  22. Hi @amitceder, I don't quite know what you mean by it behaved the same prior to rebooting, but I confirmed with the design engineer who created Adept that Adept will not initialize on any UltraScale+ boards from Xilinx. Let me know if you have any questions. Thanks, JColvin
  23. Hello @amitceder, What platform are you attempting to use Adept and the JTAG HS3 with? Thanks, JColvin
  24. Hi @electronic, I have sent a you a PM about this. Thanks, JColvin