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Everything posted by JColvin

  1. Hi @tt12345678, Yes, some of Vivado IPs have changed over the years and versions, especially since 2015.1 so upgrading them to newer versions can be tricky. For what it's worth though, Digilent has a set of materials for working with Vivado/Vitis 2020.1 available here: https://reference.digilentinc.com/reference/programmable-logic/guides/start. Thanks, JColvin
  2. Hi @Marcel, What board are you using? I don't believe Digilent has any FT231X devices that I recall. Thanks, JColvin
  3. Hi @Ken.jones, I have moved your question to a more appropriate section of the forum. I may be misunderstanding what you are asking, but you can have some of the digital pins be inputs and some be outputs and control them independently with the Logic Analyzer tool and the Patterns tool, respectively. Is this what you are asking about? Thanks, JColvin
  4. Hi @ezhanga, I have moved your question to a more appropriate question of the forum. To make sure I understand your goal, you are wanting to develop a custom application to interpret 20 bits of data in serial? Thanks, JColvin
  5. I used 2019.1 for both Vivado and SDK (not Vitis). The vivado-library I used as my IP repository I downloaded from this page, https://github.com/Digilent/vivado-library. I believe you could also use the 2019.1 release version that is available on the right-hand side of the page, though I haven't specifically tested it since I have a local copy of the repository that I keep up to date with the master instead. Let me know if you have any questions or run into issues. Thanks, JColvin
  6. Hi @rzsmi, If it's not showing up with lsusb and the same cable is successfully being used with other boards, then I suppose the USB controller on the Nexys 4 DDR has become damaged somehow, though I'm not certain how this might have happened. If you want, I can work with you to see about an RMA, though it will ultimately be the sales team decision (presuming you purchased it directly from Digilent as opposed to a distributor) if they decide to grant the RMA or not depending on when it was purchased. Thanks, JColvin
  7. Hi @specpro30, I'm not certain what else to suggest if refreshing the BSP sources and rebuilding the project in SDK does not make them go away. I found a way to upload the Vivado project archive that I used to create the Vitis project I linked earlier; it is available for download here. Thanks, JColvin
  8. Hi @hep77, FreeRTOS could work, though note that the last official Microblaze design for it (link) was in 2014.4 with a Kintex 7 chip that requires a paid Design Edition license. Otherwise, I would probably attempt to a list of different tasks that get executed when a particular character is received, similar to how the Nexys Video HDMI demo does it in it's DemoRun function: https://github.com/Digilent/Nexys-Video-HDMI/blob/master/sdk/appsrc/video_demo.c. Thanks, JColvin
  9. Hi @Han_newbie, I personally haven't used the Spartan 3E or ISE 14.7, so I won't be of much help, though it doesn't help that the Spartan 3E's were originally sold in 2006. I took a look at the Ethernet sections in the two Xilinx User Guides for Spartan 3E's that Digilent used to sell (link1, link2) and there appears to be an IP core available, though it through EDK which requires a paid license from Xilinx based on what I know about it. I found a couple of Xilinx threads that might be helpful to you though (link1, link2). I'm sorry I couldn't be of more help. Thanks, JColvin
  10. Hi @KKING, So much for the review process on Digilent's end. I'll get it updated today. Thank you, JColvin
  11. Hi @mubasheer, It says in the GPIO section of reference manual of the JTAG SMT2 NC that the output buffers for the GPIO pins are disabled, placing the signals into a high impedance state and remain disabled until an application enabled DPIO Port 0 and configures those pins as outputs, so you do not need to connect them if you do not plan to use them. As far I know, non-Zynq devices do not have a PS_SRST_B pin to connect to. If you want a more general purpose programmer similar to the JTAG SMT2 NC that is more portable, I would recommend taking a look at the JTAG HS2 or JTAG HS3
  12. Hi @Anuvab Nandi, Presuming you are referring to where I had said Arty A7, then yes; in that case it is referring to the same board as the Arty A7-35T. Digilent also has a -100T FPGA version of the Arty A7 with similar demos on that same Resource Center, but otherwise has the same layout and design as the Arty A7-35T, so I usually group those two boards together as "Arty A7". Let me know if you have any questions. Thanks, JColvin
  13. Hi @mubasheer, I presume you are referring to GPIO2 as there is not a GPIO3 on the JTAG SMT2 NC. I'm not able to really answer the question on how do I build a "universal programmer", partially because I don't know what boards and devices you are including in that phrase. On a different line of though, if you want the programmer to be universal, would you exclude Zynq devices by not connecting to the ps_srst_b pin? Thanks, JColvin
  14. Hi @Pavel_47, Not through the existing board files and Zynq configuration as is, no. It's possible to set up a bridge between the PS and the PL to get UART working, though that will require some additional work with AXI and configuring the hardware and constraints file. There are a couple of threads on this here and here. To be fair, it does say on the workshop page that an Arty S7 is needed to participate in the workshop. I don't know what all techniques and approaches will be used in the workshop as Digilent is not a part of the workshop series (outside of the hardware being used),
  15. Hi @JNestor, The reason that SW8 and SW9 (T8 and U8) are set to LVCMOS18 rather than 3.3V CMOS is because those two pins are connected to Bank 34 which contains all of the pin connections for the DDR2 chip which operates at 1.8V. Banks can only be set a single voltage, so the switches are stuck being at 1.8V CMOS rather than 3.3V like the rest of their friends. Does Vivado create an actual error that prevents bitstream generation or is it a type of warning instead? Thank you, JColvin
  16. Hi @specpro30, Turns out I was wrong on my comment about being able to use newer versions of the Vivado library and still have them work on older versions Vivado/SDK; that particular statement is only true for modules/IPs that are compiling correctly, or at least when I ran the SD project in 2019.1 with the v2020.1 library, I encountered similar errors in SDK 2019.1 that I was not able to readily resolve. I apologize for the confusion; I'll edit my old post to avoid confusing future readers. After changing the IP repository back to the local master (and regenerating the bitstream jus
  17. Hi @Marco Jassmann, I apologize for the delay. I have sent you a PM. Thanks, JColvin
  18. Hi @sowkarthika, Is your Analog Discovery 1 connected directly to a USB port on your machine, a (powered) USB hub, or something else? What version of the WaveForms software are you running and what OS are you using (it looks like Windows 10). Thanks, JColvin
  19. Hi @jean, I'm not sure I understand your question. Are you wanting to know different aspects of an IP in general are occurring at different frequencies? And how to know if an IP is connected to a clock or not? Thanks, JColvin
  20. JColvin

    ADC FPGA connection

    Hi @Norbert96, Well, based on the comment in the code and briefly looking at the datasheet, I would think that is their chosen Verilog implementation of how they are taking the output of the sinc filter at different decimation rates, with the bitsize of the output increasing as the decimation rate increased. This is explained a bit more on the previous page of the datasheet to where you found this code snippet. Thanks, JColvin
  21. Hi @wangmengsail, The folks on the NetFPGA SUME mailing list will be best able to help you with SUME applications as they maintain the materials and GitHub for it. You should already have access to the mailing list when you signed up to get access to the GitHub materials. Let me know if you have any questions. Thanks, JColvin
  22. Hi @wangmengsail, The folks on the NetFPGA SUME mailing list will be best able to help you with SUME applications as they maintain the materials and GitHub for it. You should already have access to the mailing list when you signed up to get access to the GitHub materials. Let me know if you have any questions. Thanks, JColvin
  23. Hi @rzsmi, The listed order of pins on a constraint file does not matter, so long as the required pins being declared are present, that's all that is needed. As for the discrepancy in pins, .xdc files don't list GND and 3.3V connections, only connections to GPIO and clock lines. As noted in the reference manual, some of the individual pins on the MIPI CSI-2 connector are actually connected to two separate FPGA pins as per XAPP894. If you count all of those doubled up pins and other "single" GPIO pins, you will note they add up to the same 16 pins that are listed in the .xdc file
  24. Hi @hep77, I don't quite know what you are asking. Are you wanting to be able to reprogram the FPGA from command line with a pre-existing design? Or are you wanting to configure and control the FPGA while it is already powered on? Either way, we don't have any direct examples of controlling the FPGA over serial. In principle, you could use xuartlite directly (as opposed to stdout/stdin) to read incoming data and perform a pre-defined function based off of that, but that wouldn't be using a Command Line Interface. If you are wanting to control the board and have it run a variety
  25. Hi @tt12345678, This is because Digilent did not create the Zedboard .xdc file that is present on the Digilent GitHub; Avnet did. We did not change this file to the Digilent styled format in the interest of maintaining compatibility with official Zedboard material that exists in various places (on Avnet's website, zedboard.org, etc.). The clock line is on line 82 on the Zedboard .xdc. You can then add your own create_clock statement after it if you want to; I'd probably use the same one listed in the Zybo Z7 xdc files on line 9 (https://github.com/Digilent/digilent-xdc/blob/master/Zy