JColvin

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Everything posted by JColvin

  1. Hi @moha, I would probably start with UART since it already has the option to interpret RS232 signals. These other forum threads may be of interest to you as well: Thanks, JColvin
  2. Hi @djiang, I took a look at the Zedboard kit list on the Digilent store and can confirm that this Male Micro-B to Female Standard-A USB adapter is included by default, though I have no idea why it is included because as you mentioned you need a non-typical male type A to male type A USB cable to use this adapter. Maybe it was included so people could more easily use a flash drive with the USB OTG connector. If the COM port (COM3 as shown in your screenshot) appears after connecting J14 to your host computer, then that's a good sign that the serial communication is working as intende
  3. Hi @Alessandro Reineri, What version of Vivado are you using and which particular release did you use for the Arty Z7-20 demo? Thanks, JColvin
  4. Hi @PatrickTX, I presume that when you say the FTDI drivers are installed that you also mean that you installed the cable drivers as part of the Vivado installation (Xilinx answer record with some instructions here if you have not done that: https://www.xilinx.com/support/answers/59128.html). Since you mentioned a COM port, I'm guessing you are using Windows 10 with Vivado 2021.1? Does anything appear in the Windows device manager under the Universal Serial Bus Controllers dropdown when you connect the Cmod S7? Some other things to check would be to try a different USB cable (some ca
  5. Hi @Sergey, I have sent you a PM with instructions. We have chosen not to post the application because much like FTPROG, it is very easy to overwrite the EEPROM on other chips and as far as I know not all device manufacturers have a way to restore their device. Thanks, JColvin
  6. Hi @strahd, I have sent you a PM regarding licensing. Thanks, JColvin
  7. Hi @bhysjulien, I apologize for the delay; I have moved your question to a more appropriate section of the Forum where the engineer more familiar with the WaveForms SDK material will be able to see and respond to your question, since I'm not sure what the issue might be since you already confirmed that just running the WaveForms GUI directly measures the expected results on the two oscilloscope channels. Thanks, JColvin
  8. Hi @ABwalker, I have moved your question to a more appropriate section of the Forum. I do not think there is a way to completely customize the buffer allocations. Based on the screenshot I'm guessing you are using the Analog Discovery 2? Thanks, JColvin
  9. Hi @Eric888 and @strahd, I have sent you both a PM. Thanks, JColvin
  10. Hi @djiang, Normally Avnet (or maybe element14) would be good contacts for troubleshooting their guide materials, though it also doesn't help that the zedboard.org website seems to be down. I don't have Windows 7 or a Rev F of the Zedboard, but I'm guessing you do not see a line item of "USB to UART Adapter" in the Universal Serial Bus controllers dropdown in the Windows Device Manager? Otherwise what I probably attempt to do would be see if you uninstall or otherwise update the driver that's apparently listed as 'other element' in your system. Thanks, JColvin
  11. Hi @Eric888, Oh, I didn't realize there was such an adapter available from Xilinx. Using J17 (the unloaded 6-pin jtag header) should not interfere with J12; you can simply leave the micro USB connector on J12 not attached. It's purpose was to provide the USB to JTAG connection circuitry, but if you already have that functionality through the Xilinx Platform cable, then J12 is not needed. Let me know if you have any questions. Thanks, JColvin
  12. Hi @Jonboy, I have sent you a PM. Thanks, JColvin
  13. Hi @Eric888, The Xilinx Platform Cable USB II is a 2x7 connector rather than the 1x6 header that is present on the Nexys Video. So you would need an adapter that accounts for the pin orientation changes if you wanted to use the Platform Cable, though I haven't seen such an adapter that also accounts for the difference in pin layout. If you are just wanting to connect to the board to load designs, you can use a micro USB cable (that isn't charging only) on header J12. Serial/UART communications are available through a second micro USB connector on J13. Let me know if you have any
  14. Hi @Diana52, I would recommend taking a look at these two Xilinx forum threads: link1, link2. Thanks, JColvin
  15. @attila do you the correct file that should be chosen in this situation? Thanks JColvin
  16. Hi @LYZERO, I have sent you a PM. Thanks, JColvin
  17. Hi @Troglobyte, It looks like your Block design does not have anything in it, though it seems you figured that out from based on your other forum thread: For future reference though, Digilent has a guide on creating block designs for Vivado which includes both Microblaze and Zynq based designs available here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi. Thanks, JColvin
  18. Hi @VerticalFarmingStudent, Digilent does not have any further information about this demo. The material (or lackthereof) was created by a former intern about a year back which to my understanding was porting some of the Xilinx AI materials to the Zybo Z7, but unfortunately they did not create any documentation associated this demo, so we've removed this under construction page from our Wiki to prevent further confusion. I don't think Xilinx has a lot of up to date details on SDSoC as they have moved away from that towards Vitis AI instead, https://www.xilinx.com/products/design-tool
  19. Hello, Mario785 is correct that the schematic will be the best source of material to find this information. The Cmod A7 15 schematic can be found here: https://reference.digilentinc.com/_media/reference/programmable-logic/cmod-a7/cmod_a7_sch.pdf. Thanks, JColvin
  20. JColvin

    NetFPGA-1G-CML

    Hi @zygot, I'll have to ask about the best way to force Vivado to obey, but regarding the transceiver/PCIe block locations, is figure A-5 page 350 on UG476, https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf#G10.276349, what you are looking for (presuming you are asking about the Kintex 325 on the CML board)? Or did I misunderstand the question? Thanks, JColvin
  21. JColvin

    NetFPGA-1G-CML

    Hi @zygot, To confirm, since I can't quite tell from the way you phrased it, the provided trace lengths did detail the rx_ctl and rxd traces you needed, correct? As far as I can tell from the RTL8211E datasheet, the RXCTL pin is on the same pin location as RXDV (for a different pin package) which both have the pin name of PHY_AD2, and the trace length document seems to list the RXDV_X trace lengths. Thanks, JColvin
  22. Hi @dmeads_10, I asked about this and was provided the attached datasheet; I was told though that you might have some trouble being able to source this, or at least I wasn't personally able to find the any sort of exactly matching part on the manufacturers website (or at least the list of heatsinks for Xilinx chipsets doesn't list a SFVC784 package, http://www.malico.com.tw/index.php?option=com_content&view=article&id=416&Itemid=148&lang=en) though the datasheet does provide all of the dimensions of the part. The thermal paste should be generic as far as I understand
  23. Hi @meakerb, I've always pronounced it Zee-bo because it's a Zynq board, but there isn't any official confirmation on that. I asked our Marketing Manager about it and he pronounces it both ways, so that's a thing. I guess the tl;dr is pronounce it however you like, but there's also an official poll for the pronunciation now: Thanks, JColvin
  24. JColvin

    NetFPGA-1G-CML

    Hi @zygot, The Rev F schematics are available on the 1G CML Resource Center (https://reference.digilentinc.com/programmable-logic/netfpga-1g-cml/start). I asked about the trace lengths and got some details that I have attached. I don't know exactly which signals you were looking for in particular. In terms of support, what I have been told (at least this was the case last year) is that Digilent will do some hardware error support, but if you are not able to get help from the NetFPGA mailing list (links for it are available here: https://netfpga.org/site/#/systems/2netfpga-1g-cml/supp