• Content Count

  • Joined

  • Last visited

About JColvin

  • Rank
    Forum Moderator
  • Birthday April 22

Profile Information

  • Gender
  • Location
    Pullman, WA

Recent Profile Visitors

15010 profile views
  1. Hi @J995, I asked another engineer to take a look at this since they had a Pmod Color with them at their home. They let me know that when they created a new blank application in Vitis (2019.2 version, I don't know what version of Xilinx software you have) they were able to get the attached project I provided them (it uses the Zybo Z7-10 with Pmod COLOR on JA, and with external buttons and switches matching what you have in your block design). We'll be able to provide some better details on this tomorrow. Thanks, JColvin ColorZ710-192-Forum.ide.zip
  2. Hi @Joe_01, I've asked another engineer to take a look at this. They let me know that should be fairly straightforward to upgrade a baremetal design to a newer version (provided dma stuff hasn't changed drastically) but we've been wrong before. They probably won't get the opportunity to test this out until next week though. Thanks JColvin
  3. I will let the Product Manager for the Digital Discovery that there is some level of demand for this type of cable. Thank you for your feedback. Thanks, JColvin
  4. Hello, I'm not able to readily comment on the other material, but you are correct that the V- and W2 are at other end of the pin bank since that is the underside view of the board. Those pins should instead be DIO 11 and DIO 12, respectively. Thanks, JColvin
  5. Hi @jfrenzel, Yes, you can do the same flow with original Zybo as well. We have a general guide on how this might be done in 2020.1 available here: https://reference.digilentinc.com/reference/programmable-logic/guides/getting-started-with-ipi. As a clarification note though (I don't know if it affects you), a number of our Pmod IPs are not working with the 2020.2 release version of Vivado; something changed in the Xilinx material and the engineer who typically maintains the Pmod IP demos hasn't gotten to debug and update them to a hierarchy structure. They still work on 2020.1 and ea
  6. Hi @NorthTech, I have moved your question to a more appropriate section of the Forum where the engineer most familiar with the AD2 and the WaveForms software will be able to see your question. Thanks, JColvin
  7. Hi @Alen Toji, I would recommend taking a look at this thread: From my understanding, MATLAB has a way (linked in the forum on the MATLAB page after the table of listed supported boards) for you to add other boards to their system generator so that they are supported. Digilent has not specifically worked with the MATLAB System Generator or done hardware co-simulation, so we will be of limited help in this regard. Thanks, JColvin
  8. Hi @DavidLee1997, I apologize for the long delay. I do not believe we have any double female ended keyed connectors available for the Digital Discovery. I attempted to up some sort of similar connector that could be used since the pins have a 100 mil pitch, but was not able to easily find such cable (at least not without doing a lot of digging through various distributors website listings). As an alternate solution, I do know that an unkeyed 2x6 connector that would be compatible (we use it on different Digilent boards) would be a 929975-01-06-RK from 3M. You could then attach a
  9. Hi @brahmi, Digilent doesn't make the Z7-706 board or the atmega128 nor Xilinx's XSPI library, so we won't be to offer any specific help in terms of the hardware or intricacies of the software since Digilent hasn't made any examples using Xilinx's AXI Quad SPI IP core in slave mode. The engineers on the Xilinx forum may be able to offer some more specific advice regarding their IP and provided example; it looks like there might be a couple of relevant forum threads here and here. Thanks, JColvin
  10. Hi @shyams, Normally in software you would create a variable to have a last known state (which for something like an external I/O device) can usually be predetermined and compare the last known state to the current state. I looked more into the AXI interrupt controller IP (Xilinx PG099) and learned that by default level detection is used, which might be the reason the ISR is occurring multiple times, though supposedly the interrupt handler should clear the interrupt after it is serviced for level driven interrupts. Based on what you are describing, you'll probably want Edge driven in
  11. Hi @Dylan B, The smaller black ones on the Arty Z7-20 specifically are from Kang Yang, model number RF6-5. The normal clear hemisphere ones on most of our boards are from 3M, model number SJ-5306. Thanks, JColvin
  12. Hi @Youni, Like @zygot mentioned the various Arduino add-ons can work, but you'll be needing to do some extra work in advance to check compatibility and connectivity options. Digilent has championed the Pmod connector, but not every sensor out there is directly mechanically or electrically compatible. The main things I would be checking (presuming that I'm fine with connecting individual wires to available I/O pins on the Nexys A7 100T) would be if the sensor or actuator is 3.3 V compatible and what the available software support looks like. If you end up finding out that it will be
  13. Hi @gnuarm, Are you referring to the JTAG programming cables? I was intending to link you to a page showing their differences since I've looked at many times over the years, but of course now I can't find it. The closest I can find is the table in one of their Reference Manuals here: https://reference.digilentinc.com/reference/programmers/jtag-hs3/reference-manual#programming_solutions_comparison_chart. It doesn't include all of them, but the SMT2 and SMT2-NC will match the specifications for the HS2, and the same is true for the SMT3-NC and the JTAG-HS3. Let me know if I did not gue
  14. Hi @Shifali N, I'm not certain if I am interpreting all of your questions correctly, but I'll see what I can do. 1. It will depend what you plan on interfacing with and what your system can handle. Mic levels are "weakest" in terms of voltage amplitude and usually need some sort of amplifier to bring it up to Line levels so that it can be processed. Speaker levels are much higher in amplitude and usually need an amplifier when coming from a system board. 2. Based on the description of the two datasheets for the ICs present on the Pmod I2S2 (https://www.cirrus.com/products/cs5343-44
  15. Hi @souvlaki, I apologize for the delay. My understanding (I'm likely not entirely correct) is that the default heap size set by the linker script (0x800 or about 2048 bytes is what I'm seeing) is the limiting factor here. You can increase the available heap by putting something like this (as explained in this old chipKIT forum thread) at the top of your program: #define CHANGE_HEAP_SIZE(size) __asm__ volatile ("\t.globl _min_heap_size\n\t.equ _min_heap_size, " #size "\n") CHANGE_HEAP_SIZE(0x5000); extern __attribute__((section("linker_defined"))) char _heap; extern __attribute