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Everything posted by JColvin

  1. Hi @Tonym, I loaded up the LabForms VI on LabVIEW 2014 and was in general able to successfully run it as advertised from the Instructable I linked before, and I was able to adjust the timebase on the Waveform Generator, but it does have it's own set of caveats. What I ended up doing was going to the block diagram and double clicking on the two Simulate Signal Express VI's that are towards the bottom middle of the block diagram. There you can change the Samples per second and the Number of Samples (will currently have the automatic box ticked and be set at 100000); with the default configuration of 250 MHz and 100000 samples, this leads to a total time of 0.0004 seconds, which is what you see on the WaveGen graph. You can untick the automatic box and increase the samples, but you will likely be encountered with an error that says the system may not perform as you expect; be sure to the click the "Use Anyway" button rather than the reconfigure. When I first clicked reconfigure, an error kept popping up saying the system couldn't run (or something similar) every time I closed the error, effectively softlocking me out of LabVIEW and forcing me to use the task manager to shut down LabVIEW. The "use-anyway" option let me run the VI and did work as expected, but as I was warned by LabVIEW, the system definitely did slow down when the VI was running. You can slow down the sample rate from 250 MHz, though I don't know how much that will impact your intended application (especially at higher frequencies). So not an AD2 problem per se, but more of a limitation with what sort of configurations have been implemented into the VI's (since the VI's just call existing WaveForms SDK functions). Thanks, JColvin
  2. Hi @Eric Raymond, With regards to the first question, I would say it's best to go both ways (not plug into a powered Cmod and not power a plugged in Cmod), since you are relying on a single diode to prevent any back-powering problems that could arise (as opposed to a jumper setting to choose your power source). You may be able to just remove the D1 and have it work out, though I don't know all of the ramifications with regards to powering the FTDI chip. You would also need to make sure any grounding between the input to the USB and the external power are connected to prevent voltage differences and issues there. However, if you are just wanting to power and have the Cmod A7 run a dedicated project, you can always load the flash on the Cmod A7 and every time the Cmod A7 is powered on it will automatically load the flash project. There are a couple of tutorials on this for the Cmod A7 Resource Center. The schematic page for the FTDI chip (the "This page intentionally left blank" one) is proprietary. You can send an email to support dot digilent at ni dot com to request these details though. We have a 3D model (.stp) for the Cmod A7 available on it's Resource Center on the right-hand side labeled as 3D STEP with a file name of cmod_a7.zip. There are some more dimensions about the Cmod A7 available on this thread as well. Let me know if you have any questions. Thanks, JColvin
  3. Hi @stef, Could you post your WaveForms project and script that you are using? I'm not certain what all of the time bases are on the logic analyzer screenshots and when each of your patterns are triggered. I'm not certain what you are thinking by your statement of "Maybe it's not possible to write and read this DIO's at the same time", but in general you would not want to assign the same wire to be both an input and an output simultaneously, you would instead want the output wire (from the pattern generator) to go a different wire as a logic analyzer input, but again I'm not certain of your physical setup. Could you attach a picture of your setup? Thanks, JColvin
  4. Hi @Yacov Cohen, Can you explain more what you mean by "not working"? Thanks, JColvin
  5. Hi @Yacov Cohen, Did you use the new .ino file that I had posted earlier? It adjusts the appropriate functions to match the new style of function (which requires a boolean parameter in the interest of making it so that you can enable or disable a bit in the device); I've adjusted the .h file so that it presumes a default parameter of true (which is what you would presumably do when calling the function anyway. Thanks, JColvin AD7193.h
  6. Hi @Yacov Cohen, Apparently I can't even select the correct library files; after double checking, these are the correct library files (as opposed to previous ones). I'll update the previous post as well to help prevent confusion. I when I ran it on an Arduino Uno (rather than a Digilent uC32), I didn't get the registers to read back as expected, so I'll need to double check the SPI functions used since I remember some of them use manual CS line manipulation and others do it via the library functions. Thanks, JColvin AD7193.cpp AD7193.h
  7. Hi @Tonym, I responded to your other thread here. Thanks, JColvin
  8. Hi @Tonym, The people who designed the AD2 to LabVIEW toolkit are no longer at Digilent so we do not have a local resident expert in that sense. What version of LabVIEW are you using; my understanding is that the toolkit and VI's were only designed for LabVIEW 2014 and LabVIEW 2016. Additionally, have you gotten the chance to follow this setup with LabForms? Thanks, JColvin
  9. Hi @mortuzahasan, I apologize for the delay; if you are already have the test signals being generated through 4 wires from the external JTAG dongle, you might want to look at the Pmod LVLSHFT since that can receive the four signals through wires and then have them sent out to a Xilinx styled JTAG header. Admittedly, I am a little confused at what you are hoping to accomplish though since the diagram you provided shows the flow going back through the JTAG SMT2 which I believe already has the USB header and is integrated into your FPGA system. Are you wanting to have two separate programming routes to two different locations on the final board or two different inputs to the same output? I've tried to illustrate what I mean below: Two separate programming routes: JTAG SMT2 --> Xilinx FPGA spot 1 External dongle --> JTAG HS2 --> Xilinx FPGA spot 2 Branched input to single location: JTAG SMT2 ---------------> Xilinx FPGA ^ External dongle --> JTAG HS2 -->^ Or was the illustration you gave with the HS2 talking to the JTAG SMT2 accurate? The HS2 and SMT2 are both designed to take the datastream over USB and convert it to a usable data format for the Xilinx FPGA; I don't believe either of them will just let pre-made signals pass through. Thanks, JColvin
  10. Hi @irfiee, I updated the libraries a bit more since the registers were not being manipulated correctly; I have attached the relevant library files and sketch for it as well. Thanks, JColvin AD7193_VoltageMeasurePsuedoDifferential_Example.ino AD7193.h AD7193.cpp
  11. Hi @Yacov Cohen, I have attached the new files that I worked on; I believe the registers are all correctly manipulated now, though I changed a couple of functions to have them make more sense (like adding a boolean parameter for whether or not the pseudo bit is enabled. Let me know how it goes. Thanks, JColvin AD7193_VoltageMeasurePsuedoDifferential_Example.ino AD7193.h AD7193.cpp
  12. Hi @AndrewSM, Welcome to our Forums! Thanks, JColvin
  13. Hi @Pavani Ganisetti, You could use that module. The way I would probably set up such a system would be to put the relay on it's own separate board (such as a breadboard) and connect jumper/fly wires from the Zedboard to the relay board and on the outputs of the relay use wires to connect to your light and motor as appropriate. An example of how this connection might generically look can be found on one of the images in step 10 of this Instructable. Thanks, JColvin
  14. Hi @Mettulski, I have moved your thread to a more appropriate section of the Forum where engineers much more familiar with the WaveForms software can see and respond to your question. Thanks, JColvin
  15. Hi @Yacov Cohen, I finally figured out the issue. The problem is that every function that sets a register value, including the calibrate function, pulls from the array of register map values that are globally declared at the top of the AD7193.cpp file, adjusts only the bits that the function needs to, and then applies the changes. The problem is that none of these functions read what the current state of the registers are (they all assume it is the default state), so each Calibrate, SetPsuedoDifferentialInputs, SetAveraging, etc., overwrite any and all previous changes. What each function needs to do instead is to read the appropriate register directly from the chip, make changes to the bits of interest, then reapply the changes. This can be done with the GetRegisterValue function; I'll see if I can get that fixed tomorrow. Thanks, JColvin
  16. Hi @svet-am, If it gets properly verified from our content team, then it's a possibility, but our content manager is out of the office until January or so (and will probably have a backlog of stuff to catch up on), so it may be a bit before it gets verified/approved since we (Digilent) like to try to make all of our content consistent with itself for each release cycle. So, I guess the answer is a solid "maybe". Thanks, JColvin
  17. Hi @Pavani Ganisetti, Yes, you would need to then add some external circuitry connected to the two GPIO pins in order to make the motor and LED work. I would strongly recommend using a transistor to control the motor as the pin from the FPGA will not not provide enough wattage (both in voltage and current) to successfully drive the motor. You will also likely need some sort of external power source to power the motor in general. In terms of driving the motor, you will probably want to use PWM (perhaps through the AXI timer IP from Xilinx) or a similar technique to control the FPGA pin that will then "turn on" the transistor at appropriate intervals to make your motor run at the desired speed. If you are wanting to drive the motor both directions, you will also need to implement an external H-Bridge and add an additional GPIO signal to gain the required secondary input for that setup. Good luck, JColvin
  18. Hi @bnz, I don't know if this is the case, but this thread may be of help to you. Thanks, JColvin
  19. Hi @kursatgol, Based on the previous posts provided in this thread, Vivado 2018.1 does correctly support the XUP USB-JTAG Programming Cable. The problem is that the Xilinx installer for the cable drivers (at least for Windows 10) does not work correctly, so those drivers needed to be deleted and manually installed in order to work correctly. On Linux based systems the cable drivers are not installed automatically so you have to manually install them yourself through a series of commands (as described in Xilinx's UG973). If you have already done those steps, we (Digilent) do not have any other advice as to what you can try aside since we do not offer any formal support for getting devices to work in vitual machines; the engineer I mentioned before only happened to try VMware since they already had it installed and it worked for them when they followed the installation instructions from Xilinx documentation. I'm sorry I couldn't be of more help. Thanks, JColvin
  20. Hi @irfiee, If you are not already, I would also recommend using the libraries I posted on this thread since it defines and uses mPolarity whereas from what I remember other libraries online did not use this parameter. Thanks, JColvin
  21. JColvin

    DMC60C CAN communications

    Hi @adamkolesar, I recommend taking a look at this page as it contains all of the documentation for the DMC60C API; the specific page for the WPI functions can be found here. Let me know if you have any questions. Thanks, JColvin
  22. Hi @kursatgol, I suspect @Edwardz followed these instructions for their Windows 10 machine. Since we haven't used VirtualBox we don't have any advice specific to that, but let me know if you have any questions. Thanks, JColvin
  23. Hi @ENGR498, I believe you can find an example using the Digital IO within the examples folder at "\examples\DigilentWF\Digilent_WaveForms_Digital (DIG).vi" inside of the LabVIEW Installation path as per the Digital I/O section on LabVIEW's Getting started guide here. They also have a block diagram showing the basic structure for an array of connected inputs and outputs. Let me know if you have any questions about this. Thanks, JColvin
  24. Hi @kursatgol, The engineer let me know that he has only ever used VMWare. In terms specific installation for Vivado 2018.1 on a Centos 7 64-bit they did the following: <start> All I had to do to get the XUP USB JTAG cable to work was follow the instructions in the "Installing Cable Drivers" section of Xilinx UG973. Essentially all you have to do is go to a particular directory (“<Vivado Install Dir>/data/xicom/cable_drivers/lin64/install_script/install_drivers/”)and execute an install script. On my system this required the following steps: 1. Execute "cd /opt/Xilinx/Vivado/2018.1/data/xicom/cable_drivers/lin64/install_script/install_drivers/" 2. Execute "sudo ./install_drivers" After that you simply run Vivado and use hardware manager like normal to connect to the cable. 1. Execute “source /opt/Xilinx/Vivado/2018.1/settings64.sh” 2. Execute “vivado” to launch the application. 3. Open hardware manager and click auto connect. Vivado 2018.1 had no problem finding and configuring the Zynq 7020 on the Zed board. </end> Thanks, JColvin
  25. Hi @Chandana, I have moved your question to a more appropriate section of the forum where the engineers much more experienced with the Analog Discovery 2 look. I presume you are using SDK to program the digital IO channel? What version of Waveforms are you using and did you try out the Digital IO example that comes with WaveForms SDK in the example folder? Thanks, JColvin