JColvin

Administrators
  • Content Count

    4437
  • Joined

  • Last visited

About JColvin

  • Rank
    Forum Moderator
  • Birthday April 22

Profile Information

  • Gender
    Male
  • Location
    Pullman, WA

Recent Profile Visitors

14212 profile views
  1. Hi @runsler, As of this posting, I haven't heard any updates about the FMC adapter to support ultrascale+ devices as of yet, though I believe it is still in the works. I'm sorry I could not provide better news. Thanks, JColvin
  2. Hello, I took a look on the Digilent servers for the OpenScope MPLAB X source material, but I wasn't able to find it. I can find the OpenLogger source project on the server, but it's already up on it's GitHub page: https://github.com/Digilent/openlogger. Thanks, JColvin
  3. Hi @13qqq, We are taking a look into this error. I was told that this may be related to some MIG problems with new versions of Vivado. Thanks, JColvin
  4. Hi @yadus, Those of us at Digilent haven't worked specifically with the ZCU102 board, but there are a couple of threads on transferring data between PS and PL here and here. Thanks, JColvin
  5. Hi @Mike.H, You are correct, Figure 2 is incorrect in it's placement of the front porch, and it should be before the sync pulse as shown in Figure 3; good catch. I will see if I can get this image (and all of the other images in other pieces of documentation) corrected. Thanks, JColvin
  6. Hi @Giuliana, I have not personally done this but based on page 33 of the datasheet, https://www.analog.com/media/en/technical-documentation/data-sheets/AD5933.pdf, "To achieve system accuracy from the 0.1 kHz to 1 kHz range, the system clock needs to be scaled down from the 16.776 MHz nominal clock frequency to 500 kHz, typically. The clock scaling can be achieved digitally using an external direct digital synthesizer like the AD9834 as a programmable divider, which supplies a clock signal to MCLK and which can be controlled digitally by the nearby microprocessor.". If you wanted t
  7. Hi @fp99, You don't need to do anything particularly different. We have a demo for the Pmod VGA on the Zybo Z7 that uses two differential Pmod ports on the Zybo Z7 (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pmod-vga-demo/start) and looking at the .xdc for the project (https://github.com/Digilent/Zybo-Z7-20-Pmod-VGA/blob/master/src/constraints/Zybo-Z7-Master.xdc) there is not anything fancy done for those differential ports, just the normal naming of the pins to match the name of the signal used in the design. Thanks, JColvin
  8. I apologize for the long delay. Those of us at Digilent haven't worked with the OV7670 so we don't have a lot of super helpful advice to offer. The best that I will be able to do is direct you towards the FMC PCam adapter demo that we have on our GitHub, https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO, that uses the Zedboard with multiple OV5640 cameras at multiple resolutions Thank you, JColvin
  9. I apologize for the long delay. There is not a way to make the Basys 3 provide 5V from the Pmod header as that is already a set voltage by the FPGA bank. You might be able to use an external shift register to adjust the output IO signal voltages from 3.3V to 5V and then externally power the HC-SR04 with a separate 5V power supply (making sure that the grounds of the Basys 3 and the external power supply are connected), but there is not a way to do this natively from the Basys 3 itself. Thanks, JColivn
  10. I apologize for the long delay. If you are using a block design flow with the Pmod OLED IP, Vivado will automatically take care of the .xdc portion of the project for you through the Digilent Board Files. If you are manually assigning the pins, you will only need to change the names of the pins listed after the "get_ports" portion of the JB in the Basys 3 xdc file, https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#L152, to match what you name them in your design. Thanks, JColvin
  11. Hi @rt54321, Those warnings (based on my understanding) are due to your version of Vivado not having downloaded the associated Kintex part with those two boards (Kintex-7 325-T). You can get rid the warnings by either adding that part to your installation of Vivado (by bringing up the Xilinx Information Center and choosing to add parts to your installation, and then adding the Kintex-7 family) or by going to the board files folder (C:/Xilinx/vivado-boards/new/board_files in your case) and deleting the Genesys 2 and Sword listings. Personally I would do the latter as that will take a
  12. Hi @TaTo2456, I'm not certain; I wasn't able to find source files within Digilent's materials, just the .hex file which matched the one that is in available in the Max32 Resource Center. I'm sorry I could not be of more help. Thanks, JColvin
  13. Hi @TaTo2456, The source code for the bootloaders are available on GitHub: https://github.com/chipKIT32/chipKIT-digiboot. Thanks, JColvin
  14. Hi @fp99, You can use the Pmod VGA on JB and JC on the Nexys Video; although the signals on the board are differential they can still be used in a single ended fashion. Let me know if you have any questions about this. Thanks, JColvin
  15. Hi @eyz, I apologize for the delay. That line is in there for the IC1 and IC2 (the two schmitt triggers, https://www.onsemi.com/pub/Collateral/NL27WZ17-D.PDF, located prior to the N-FETs), as these ICs can only handle up to 5.5V from the host boards. If you leave JP1 disconnected (disconnecting the external power supply that can be applied to the separate J4 screw terminal from pin 6 on the 6-pin header), you can provide a 12V power supply and not hurt your board that way. I see that the reference manual does not make this clear, so I will get this updated. Let me know if you ha