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JColvin last won the day on August 3

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About JColvin

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    Pullman, WA

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  1. Hello @tuskiomi (and other curious readers on this thread), I confirmed with our Sales Manager that Digi-Key does not do any academic discounts (and for reference, very few distributors will do academic discounts; the only one that I am aware of is Trenz Electronics, but that is only for German customers. But I don't think they have any Genesys 2's in stock even if you do happen to be based in Germany). I am waiting for confirmation our FPGA Product Manager that the timeline listed on the Genesys 2 store page, i.e. boards slated to be shipping again from the Digilent store directly in September 2020, is the most up to date information. Thank you, JColvin
  2. I'm not too experienced with VHDL so I'm probably wrong, but I did see that the N number of 8-bit words listed between the HsSerializer entity listed in HsSerializer.vhd and the HsSerializer component in the HsUartTx.vhd file did not match. But I'm not sure if that difference contributes to the 16% improvement you found.
  3. Hi @Ralph Kruger, Which board do you have? Thanks, JColvin
  4. JColvin

    FPGA for a beginner

    Hi @rashimkavel7, There is a nice thread on here that discusses some of our different boards here: https://forum.digilentinc.com/topic/2576-hello-digilent-community/. As for implementing an FFT, a number of people use the IP core from Xilinx though you can do it otherwise as per these couple of threads here and here, (with many more threads on the FFT topic elsewhere on the forum). I'm not certain what you are envisioning when you say "proper linux support". Digilent has some Petalinux projects for a number of our Zynq boards but they tend to be restricted to certain versions of Petalinux. Thanks, JColvin
  5. Hi @Soham Kulkarni, I have sent you a PM with some instructions on how to restore the EEPROM. Thanks, JColvin
  6. JColvin

    CMOD S7

    Hi @BParsons, Digilent has made the choice to keep that part of the circuitry on our boards proprietary. Thank you, JColvin
  7. Hi @wpless, The Petalinux project for the Eclypse Z7 is available on our GitHub here: https://github.com/Digilent/Eclypse-Z7-OS. Thanks, JColvin
  8. Hi @Iceman2020, I apologize for the delay, it look longer than expected. I have attached the two pdfs. Let me know if you have any questions. Thanks, JColvin Statement of Volatility Cmod A7-35T.pdf Statement of Volatility Cmod A7-15T.pdf
  9. JColvin

    Cora Z7 Pmod RS485

    Hi @sverhoff, It will be more complex that to simply connect Xilinx's AXI UARTLite IP to the Pmod RS485 because that IP does not natively support the RS485 protocol. There is a patch posted on a Xilinx forum here though: https://forums.xilinx.com/t5/Embedded-Development-Tools/Feature-Request-UARTlite-with-RS485-Driver-Enable-output-signal/m-p/689335#M39324. There is also another post that may be of interest to you here: https://microelk.azurewebsites.net/ZynqLnxRS485/ZynqLnxRS485. Thanks, JColvin
  10. Hi @fkropat, I have sent you a message as well with the Digilent contact information. Thanks, JColvin
  11. Hi @rpudelko, Additionally, it looks like you are using Vitis, so I would recommend following our updated guide for this here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/2020.1/getting-started-with-ipi. Let us know if you have any questions about this. Thanks, JColvin
  12. Hi @borhan, What board are you using so I can help you restore the material? As for preventing the problem in the future, the only recommendation I have would be to maintain extra caution when configuring different FTDI devices with FTProg or other similar programmers as they, as you and many others have found out, can very easily overwrite the configuration on a different board and not everything is easily reconfigured. It's an extra step in the process, but I would disconnect boards that you don't intend to program when using these types of programmers to prevent accidents. Thanks, JColvin
  13. Hi @manboy, I asked another engineer more familiar with the Pcam about this. Thanks, JColvin
  14. Hi @BT12, I apologize for the delay. Our projects that we have for the Genesys ZU on our GitHub, https://github.com/digilent?q=genesys+zu&type=&language=, are designed to work with 2019.1, not 2018.2, though the board files should not be picky about the Vivado version. What errors do you get in the during the Run Block Automation process? And what Xilinx evaluation board are you referring to? Thanks, JColvin
  15. Hi @ennegi, I apologize for the delay. My understanding based on the ESP32 reference manual, https://reference.digilentinc.com/reference/pmod/pmodesp32/reference-manual, is that the program loaded on it is AT Instruction Firmware, which is set up in slave mode that sets the top row of pins to UART. To use the pins as a SPI header, you would need to load custom firmware that makes use of this SPI header. Updating this firmware is somewhat described on this ESP32 forum thread here: https://esp32.com/viewtopic.php?t=5136. Digilent doesn't have any custom firmware that we have created for the module. Let me know if you have any questions about this. Thanks, JColvin