JColvin

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About JColvin

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  • Birthday April 22

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    Pullman, WA

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  1. Hi @nurber3, I haven't heard any plans about a Time-Domain Reflectometer (presuming that is what you mean by TDR), though the engineer most familiar with WaveForms and the Analog Discovery Pro hardware commonly checks this forum and will be able to see your inquiry about this (they are on a different timezone though so it may be a little while before they respond). Thanks, JColvin
  2. Hi @nurber3, So I can better help you, what are you envisioning with these annotation within WaveForms? I know you can add Labels (text boxes that are overlaid on the display), Cursor lines that automatically calculate and show the current value of a WaveForm at a set point, and the Export functionality will let you add some comments and time stamps. I've attached screenshots of each of these different features (should be shown in order) that I took from the built-in Help document within WaveForms. Are you looking for a different kind of annotation? Thanks, JColvin
  3. Hi @jstander, Hmm, I would have expected Vivado to automatically update the wrapper as well, presuming when you originally created the wrapper that you kept the default selection of Vivado auto-update and manage the wrapper. Though sometimes I end up choosing to delete the wrapper, update a design, re-validate, then re-add the wrapper to make sure Vivado knew to incorporate the changes. I agree that having students make these manual changes is not ideal. Digilent doesn't have any direct references on adding software drivers for custom IP blocks. I know Xilinx has extensive (alb
  4. Hi @jstander, I apologize for the delay. I personally have not been able to generate bitstreams for most of the Pmods in newer versions of the Vivado (specifically 2020.2). I am able to generate a bitstream and successfully use the Pmod AMP2 in Vivado/Vitis 2019.2 though. With regards to updating the Pmod IPs for newer versions of Vivado, Digilent intends to have them working, but the IP maintainers haven't had time to hunt down the bug in the tcl scripts to get the IPs fixed, thanks to various higher-ups dictating their time being dedicated to other projects. Thanks, JCo
  5. Hi @James783, I have sent you a PM. Thanks, JColvin
  6. JColvin

    FFT and DDS IP core

    Hi @fatemeh, I don't know what board you are using, though Digilent doesn't have a lot of advice regarding the two Xilinx IPs you mentioned despite this. There are some threads on our forum, link1, link2, link3, that may be helpful to you though. Thanks, JColvin
  7. JColvin

    Genesys ZU

    Hi @Leo_W, The PS_REF_CLK should be simply 30 MHz as per the Oscillator and Clocks section of the Genesys ZU. Digilent, to my knowledge, hasn't created an acceleration platform for the Genesys ZU (or other Digilent boards), so we don't have a lot direct advice to offer regarding acceleration platforms. I would also recommend making sure that the serial terminal baud rate matches what is used in the design. Thanks, JColvin
  8. Hi @Brant, Welcome to the Forums! Let us know if you have any questions regarding the Analog Discovery Kit. Thanks, JColvin
  9. Hi @ebattaglia42, I apologize for the delay. There are the 1x2 pin jumpers below each BNC connector for both the Oscilloscope and and Arbitrary WaveForm Generator connectors, if that is what you are looking for. Those MTE connectors are also differential unlike the BNC connectors. There is a slide switch so you can choose which connection style you prefer. Let me know if you had any other questions. Thanks, JColvin
  10. Hi @schoechm, I'm not sure where you're getting the 3.3V from (unless you're looking at FPGA pin J15, which is attached to a bank that is powered at 3.3V). Connector J15 for the battery should be 1.8V as per page 12 on the Zybo Z7 schematic, https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf, where you can see VCCBATT_0 in the lower left of the IC19H. To be clear, I also don't know for sure if adding a battery will work, as per Xilinx AR#47565, though perhaps this does not affect production devices based on AR#47916? I'm not certain.
  11. Hi @ErosL, I have sent you a PM. Thanks, JColvin
  12. Hi @shadowcentaur, I just got confirmation from our Product Manager that there will not be any copyright issues using screenshots of WaveForms (or any photo from the Digilent Flickr account if you need some official product photos) She did request though that if possible you use Analog Discovery 2 (as opposed to AD2) and WaveForms (as opposed to Waveforms) to match the capitalization style that Digilent uses. Thanks, JColvin
  13. Hi @shadowcentaur, I'm not aware of any copyright issues for using screenshots or our provided Frtizing AD2 image, though I will double check with the Test and Measurement Product Manager. Thanks, JColvin
  14. Hi @S.P, Any of those cables you mentioned should work; if you're not certain, each of those programmers reference manuals (JTAG HS3 reference manual link as an example) has a list of supported target devices, on which the Coolrunner-II CPLDs are listed. Thanks, JColvin