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  1. @[email protected], @JColvin Thank you for your help - the problem is solved. Of course, it was my fault - but there was no problem with the SPI configuration. The reason was the Jumper 1 on the PmodCLS board - I did not connect the CS signal from my microcontroller. Without the Jumper, the CS is low all the time, so the LCD controller latches every clock edge - including the GPIO initialization state changes. At least I learned to check the schematics more carefully. Thank you again for your help, Chris
  2. @[email protected], This configuration is Mode 0, so CPHA = 0 and CPOL = 0. That's why the clock drops low before the CS (data is sent on the rising edge). The CS is high all the time (except data transmission as shown in the screenshot). Maybe the mode 0 is wrong - should the clock phase be 1 (idle in the high state)? What SPI configuration did work for you? Chris
  3. @[email protected],@JColvin, I tried once again with the logic analyzer and recorded the signal of the first transaction ("\x1b[j"), which should clear the display. Unfortunately, it clears the display but only after power on and after each 8th CPU reset. In other cases, it causes some characters to appear which correspond to the shifted data. Strange thing is that the CS signal remains high during the whole CPU reset, so there should be none additional bits sent to the controller. The clock frequency is 430kHz. In this configuration, the CS pin is controlled by the hardware, as well as the r
  4. Hi @[email protected], When I have the SPI configured in mode 0, the CS is controlled by hardware. In mode 2, the CS in controlled by software as normal GPIO. It is reset to low state before the first edge of the SPI clock and set to high after each byte transmission. I also try to keep it low for multiple bytes transaction, but with the same result. Chris
  5. Hi @JColvin Thank you for the reply. I still can't solve the issue but maybe you could confirm what should be the SPI mode for the PmodCLS. I can't find any information about this i the docummentation, but I think it may be the good point to start looking for the reason of my problem. I set the SPI clock to the lowest possible frequency for my current system clock. The scope confirms that it is about 230kHz. I tried also 460 kHz, but the behaviour is exactly the same. I have also found out that in the SPI mode 0, the string is displayed correctly after power on, but after CPU reset u
  6. Hi, I'm trying to use my PmodCLS (rev. E) with an STM32F723E-DISCO board. I connected it to the SPI port (J1 connector) and configured the SPI with CPOL=1 CPHA=0. I configured the module using the following commands: write("\x1b[j", 3); write("\x1b[0h", 4); write("\x1b[0c", 4); write("\x1b[0;0H", 6); Then I'm sending some ASCII string. The problem is that the last character does not appear on the display. I investigated it for some time and found out that it concerns also the commands. It looks like the last character from the previous transaction is received by the Pmod at