jago

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  1. In case someone is interested in this: I've successfully increased the configuration speed to 66 MHz. For this I only needed to set the configuration option "Enable the FPGA to use a falling edge clock for SPI data capture" to "YES". Now it's no problem when I put my oscilloscope's probe on the clock line. The messured frequency was about 68 MHz (due to the tolerance).
  2. You're right. I tried to be as fast as possible but I should only be as fast as I need to be. I also found out that the chip has a XIP-Mode where the read command has to be sent only once. Once the chip is in this mode the SPI master needs to start with the read address. This saves 8 clock cycles for every address change what equals 320 ns at 25 MHz. So I will follow your suggestion and implement it in logic starting at 25 MHz.
  3. Today I found this interesting article: http://www.xilinx.com/support/answers/65171.html This could be one big issue in my project. The STARTUPE2 adds a delay of up to 7.5 ns to the clock path. So even using the Xilinx AXI QSPI IP Core I could run into trouble without having constrained the I/Os properly...
  4. Hi sbobrowicz, thanks for your response. Unfortunately I didn't have the time to test some of your suggestions. Hopefully I have some time over the christmas holidays. This is correct. OK, but the SPI_If stops clocking between two consecutive transfers. I think the communication could be messed up at this point. Or is there a way to disable the clock while the SPI_If is not active without adding another delay to the clock path? I will have a look on how to add these constraints. I never had to use this. But I think it's time to learn how to deal with this important feature. I will also have a look at this. Perhaps it's better to build a new component from scratch than to modify the SPI_If. So far I didn't consider this as I thought this would add too much delay. Maybe I'm just too inexperienced in this technology. It would be great to use an existing and tested ip core. I'm thinking about how this could be designed and connected to the microblaze system to meet the access timings. Do you have some ideas what could be a good approach? Maybe I could make an AXI slave component that captures the latched address and sends an interrupt to the microblaze processor. Than the processsor reads the data at this address using the Xilinx's Quad SPI IP Core and sends it back to my component. My component could hold the data in a FIFO until the external device reads it. But (without having done some calculations) I have some doubts that this would be fast enought. The microblaze interrupt latency and the AXI bus will produce additional delay. I will play a bit with this as soon as I have some time. Or do you think it would be better to learn how to design an AXI master? I think this is much harder to implement but as a master my component could directly request the data from the SPI Core. At the moment I really don't know how complicated it is to design a AXI master. Some months ago I did the "Getting Started with MicroBlaze" tutorial and created an AXI slave for the 7 segment display. Using this slave the processor can set the values to be displayed (and their brightness) without having to handle any interrupts. This component was not too hard to implement but I have no other experience with Microblaze and AXI.
  5. OK, thank you. I'm really looking forward to the reply.
  6. jago

    Nexys4DDR Linux

    Thanks for your reply. If I have time someday , I 'll watch that.
  7. jago

    Nexys4DDR Linux

    What happened to the Embedded Linux topic on the Nexys4DDR wiki page? It was "under construction" and now it's removed. I was looking forward to see this project since I got my Nexys4DDR. What happened? Didn't the Artix7 have enough power or did Nexys4DDR have to few ressources? Regards, Jago
  8. Hi, I'm trying to read the Configuration Flash of the Nexys4DDR. I need to achieve a relatively high speed. Here is a short summary of what I'm trying to do: My design will be controlled by an external master and there is no way to delay the masters request. The start address is latched first. After that I have about 1 us until the first read request will be applied. The subsequent reads will occur in a burst with a read cycle time of about 350 ns. Each read must deliver 16 bits of data to the master. I've been thinking about the QSPI-Flash as some kind of boot rom. And now I'm trying out if this is possible. With some combination of a high Frequency, the DDR and Quad I/O feature of the S25FL128S this could be done I believe. For the first step I got the SPI-Interface itself working using the Digilent SPI_If from the Nexys4DdrUserDemo. The SPI clock is output using the STARTUPE2. I could already read the device ID and some data successfully at 25 MHz. But at 50 MHz I'm reading garbage. Then I tested the maximum Configuration Rate (4 bit width) to find out if it is only a problem of my design. The Artix7 should be able to output a 100 MHz clock on the CCLK-Pin (FMCCK). The QSPI Flash should handle 133 MHz. But for me the maximum Configuration Rate is 40. Setting the CR to 50 will cause the FPGA to never load from SPI. Also when I attach my oscilloscope to the clock pin, the configuration at CR40 fails. So, my questions are: - What is (or should be) the maximum clock frequency of the Nexys4DDR QSPI design? - Is the FMCCK = 100 MHz only valid for configuration or is this also the maximum clock for the user design? - Do I have to constraint some attributes of the QSPI I/Os to achive a high clock? - Can this be done with "normal" logic or do I have to deal with something like SERDES? I'm using Vivado 2015.4 and have applied the contraints for "Clock signal" and "Quad SPI Flash" from the Nexys4DDR_Master.xdc from Digilent. Regards, Jago
  9. Thanks a lot. You're right, Purchasing an AVR programmer only for this case is not the best solution. And I'm not planning to do something else with AVR at the moment. Nevertheless, it would be nice to get the Firmware. Maybe I buy a really cheap device (already seen some on ebay) or I could try to download the file using a FTDI FT2232. I already have a FT2232 here, but didn't build a board for it. Do you know if the AVR device is readprotected? If not, I could make a backup of the original firmware. Just in case it would not work.
  10. I installed a fresh Win7 32 bit system and I was able to install the CRII Board files and drivers. It is possible to download the CPLD demo image using CoolRunner-II Utility Window. ExPort is still showing an error, but now it is because of a missing map file and the message box () gives a hint that it could have something to do with the XILINX environment variable. I tried to set the variable to C:Xilinx (where I installed ISE), but it didn't work. Maybe the variable must be set to a subdirectory. OK, CoolRunner-II Utility Window is working. It's nice to know that there is a way to use the board if I absolutely need to. But I still would prefer a way to use the board with my 64 bit system. It's a really stupid workaround to install a whole new system. If it's totally impossible to add support for this revision to Adept, I will look for a cheap USB JTAG cable, because it will be more valuable to me than another CR-II board. Maybe a Digilent HS2 or one of these Xilinx clones selling on ebay for about 35 €...
  11. Thank you very much. Maybe I've got time to install a 32 bit system at the weekend. But I'm not sure. There are no WinXP drivers for my PC, but Win7 x86 could be worth a try.
  12. The software from the CD didn't work for me. I suppose it is because the drivers are incompatible with my 64 bit system. After the installation there are three programs in the start menu. ExPort, TransPort and CoolRunner-II Utility Window. ExPort and TransPort are complaining that dpcutil.dll is missing. CoolRunner-II Utility Window doesn't find jtsc.dll. When I connect the CPLD board no drivers are found. I tried the software with VirtualBox on WinXP (32 bit) and Win7 (32 bit). All three programs can then be started. During the installation a message is showing up that unsigned drivers are being installed. This message is not shown on my 64 bit system. But the problem is that I can not connect the USB device to the virtual system. So this seems to be no solution. Maybe I try the Windows XP Mode. If this doesn't work too I have to install a 32 bit system on a second hard drive. But this is really much effort. It would be really great if the Adept software or the iMPACT plugin could at least support the onboard JTAG programmer. The other functions of the board are not that important I think.
  13. Hello, thanks for your response. Unfortunately, I do not own a rev. F. My board is rev. D. This is not a new board. It's been some years since I bought it. At that time it came from Xilinx, but the utilities have always come from Digilent. So I hoped there was a way to get this old board back to work. Windows recognizes the board as "Digilent USB Device". When I start Adept the board enumerates as "Cr2s2" in the Connect drop down menu. The log shows the following lines: ===== Digilent Adept ===== Adept System Rev 2.7 Adept Runtime Rev 2.16 Adept Application Rev 2.4.2 Copyright © 2010 Loading board information... Warning: Could not find specific board information Default information loaded. I tried iMPACT v14.7 too. When I click on "Initialize Chain" the log shows (only copied the first 4 lines): GUI --- Auto connect to cable... INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4 INFO:iMPACT - Digilent Plugin: no JTAG device was found. AutoDetecting cable. Please wait. As a verification I tried my Nexys2 Board. It works with both Adept and iMPACT. In the iMPACT Cable Setup window, I noticed that the Port drop down shows my Nexys2 board, when Digilent USB JTAG Cable is selected. This drop down is empty when my CoolRunner-II board is connected.
  14. Hi all, I have a problem with my CoolRunner-II CPLD Starter Kit (Revision 2.0). I know this is an outdated product which is not supported by the latest version of Adept. But I had a look at the schematics of the current revision 3.0 and I noticed that the USB to JTAG controller is the same MCU like the one in revision 2.0. I'd like to know if it would be possible to reprogram the firmware of that controller and get my board to work with the latest Adept version. Or is there another solution to use the board with a Xilinx iMPACT plugin? (I use ISE 14.7 on Windows 7 64 Bit) I already tried to use the latest plugin but I can not connect. As soon as I connect my Nexys 2 Board the plugin works fine. I would be very happy if there was a way to work with my CoolRunner II without having to buy any additional JTAG cable or another Coolrunner-II Starter Kit which is almost the same like the one I already own. Do you have any suggestions for me? Best regards,jago