laikan57

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  1. I have a simple 8-3 priority encoder that uses the switches as inputs and then LEDs as outputs (valid bit + 3 bit encoded.) My UCF only has those pins defined. As you can see the 7seg seems half lit. Is there a best practice on how to set the pins on the FPGA when I am not using them for a particular project? Do I define every pin in UCF? Is there a verilog way to say just ground everything I'm not using? Thanks guys. Thanks! UCF: ## This file is a general .ucf for Nexys3 rev B board ## To use it in a project: ## - remove or comment the lines corresponding to unused pins ## - rename the used signals according to the project ## Clock signal #NET "clk" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK, Sch name = GCLK #Net "clk" TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; ## onBoard USB controller ## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin. ## 7 segment display #NET "seg<0>" LOC = "T17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = CA #NET "seg<1>" LOC = "T18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L51N_M1DQ13, Sch name = CB #NET "seg<2>" LOC = "U17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L52P_M1DQ14, Sch name = CC #NET "seg<3>" LOC = "U18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = CD #NET "seg<4>" LOC = "M14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L53P, Sch name = CE #NET "seg<5>" LOC = "N14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L53N_VREF, Sch name = CF #NET "seg<6>" LOC = "L14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L61P, Sch name = CG #NET "seg<7>" LOC = "M13" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L61N, Sch name = DP #NET "an<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50N_M1UDQSN, Sch name = AN0 #NET "an<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50P_M1UDQS, Sch name = AN1 #NET "an<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49N_M1DQ11, Sch name = AN2 #NET "an<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49P_M1DQ10, Sch name = AN3 ## Leds NET "D_out<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = LD0 NET "D_out<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = LD1 NET "D_out<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5P, Sch name = LD2 NET "D_out<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5N, Sch name = LD3 #NET "Led<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15P, Sch name = LD4 #NET "Led<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15N, Sch name = LD5 #NET "Led<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16P, Sch name = LD6 #NET "Led<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16N_VREF, Sch name = LD7 ## Switches NET "D_in<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = SW0 NET "D_in<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = SW1 NET "D_in<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = SW2 NET "D_in<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40P, Sch name = SW3 #NET "sw<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40N, Sch name = SW4 NET "Ctrl<0>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41P, Sch name = SW5 NET "Ctrl<1>" LOC = "V8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41N_VREF, Sch name = SW6 NET "Ctrl<2>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #Bank = MISC, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7 V: `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12:06:33 02/09/2015 // Design Name: // Module Name: shift_rotator // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module shift_rotator( input [2:0] Ctrl, input [3:0] D_in, output reg [3:0] D_out); always @ (Ctrl, D_in) begin case (Ctrl) // pass 3'b000: D_out = D_in; // shift right 1 2 3 4 3'b001: D_out = D_in >> 1; 3'b010: D_out = D_in >> 2; 3'b011: D_out = D_in >> 3; 3'b100: D_out = D_in >> 4; // rotate right 1 2 3 // Should re-implement this with Ctrl offsets 3'b101: begin D_out[3] = D_in[0]; D_out[2:0] = D_in[3:1]; end 3'b110: begin D_out[3:2] = D_in[1:0]; D_out[1:0] = D_in[3:2]; end 3'b111: begin D_out[3:1] = D_in[2:0]; D_out[0] = D_in[3]; end // disabled default: D_out = 4'bz; endcase end endmodule