aytli

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  1. aytli

    Zybo HDMI startup issues

    Thanks for the response, is there something I can probe on the board to see if it's being back powered or not?
  2. So I understand that the HDMI ports on the Zybo should be disconnected on startup, due to some power reflection issue. Does this problem also exist in other Digilent boards that can handle HDMI? I'm currently looking at Pynq, Arty-A7, and Nexys Video. Alternatively, if I were to somehow route a video input into the Zynq board through the 15-pin PCAM port (either from a camera or an HDMI-CSI adapter), would it have the same issue?
  3. I'm working with a computer that has a DVI video port, which I want to route into the HDMI sink of my Zybo Z7-10. I've tried using a passive splitter (DVI to DVI+HDMI) to capture the video signal going to the monitor, as a DVI to HDMI adapter to directly feed the video signal into my board. When I connect either of these to the HDMI sink, the DONE LED (LD12) on my board will light up (it looks dim, and it gets dimmer when I use the adapter instead of the splitter). This will happen even when I flip the power switch off and unplug everything including the power cable. Nothing else on the board
  4. I'm working on an HDMI processor using a Zybo Z7-20 board, with Vivado 2016.4. The starting point of this project was the HDMI demo project, using the dvi2rgb and rgb2dvi cores. Since the dvi2rgb block doesn't handle audio data, we've connected a commercially available HDMI audio extractor right before the HDMI RX port. I'm using 3 different video sources: laptop, ipod, and ipad (with lightning to HDMI dongle). All 3 are compatible with the FPGA, I've fed them each directly into the RX port and displayed them to a monitor on the TX plug. They're also compatible with the audio extractor, I
  5. Hi @jpeyron I've probed those components and got the following voltages: C222 - 5V across, I'm assuming this is the 0805 part. There's a smaller 0603 part beside it that measures 8V on one end and 3V on the other. C223 - 3.3V C229 - 3.3V C233 - 1.8V C237 - 5V C240 - 1.8V I have tried a different cable, which doesn't work. We don't have another computer with Vivado installed. Adept 2 is able to see the board, and my computer does actually think that a device is connected. When I start the hardware server in Vivado, I get the following error message: open_hw_tar
  6. I can no longer connect to my Zybo Z7-10. About an hour ago I tried to load a project on Vivado SDK, and it wasn't able to connect to the board. I restarted SDK, power cycled the board a few times, reconnected the usb cable, and also restarted my computer, and it still wasn't able to connect. I then tried using the hardware manager in Vivado to auto connect to it, and it didn't work. I've tried powering it with both the usb cable and a 5V wall adapter. I've tested the wall adapter and it's working fine. After I gave up on connecting to it, I tried to run the demo project by switching the
  7. // Dimensions of the digit images #define IMG_WIDTH 74 // MUST BE A MULTIPLE OF 2, max 128 #define IMG_HEIGHT 86 #define IMG_SIZE_PIXELS IMG_WIDTH*IMG_HEIGHT*4
  8. Short version: I have reason to believe that my RAM isn't clearing on startup. It seems to retain its old value even when I reset, reprogram, or power cycle my board. I'm also having trouble writing data to arrays. I'm working on an HDMI processor with a Zybo Z7-10 board, and I'm trying to overlay some images on my HDMI output. The images are read from an sd card on startup, and stored in the following array, where IMG_SIZE_PIXELS is 74*86*4. static uint8_t digits[10][IMG_SIZE_PIXELS] __attribute__((aligned(0x20))); My block diagram has a video mixer core connected between the vide
  9. Hi @jpeyron The DMA audio demo uses the d_axi_i2s_audio IP core, which has a S2MM output and MM2S input. The first thing I've tried was to route the output directly into the input, which didn't work. In addition, the way the C code handles recording is by configuring the DMA block to record, then telling the i2s core to store N bytes from the input into a register. The HDMI demo works by reading video data into a series of video buffers, and displaying image data from a series of frame buffers. I can make an HDMI passthrough by pointing the display output buffer to the video input bu
  10. Hello, I'm working on an audio project with a Zybo Z7-10 board (with Vivado 2016.4), and as a starting point I'm trying to set it up as an audio passthrough. I've been working off of the DMA audio demo, but I can't seem to get it to output a continuous stream. Is there a way to modify it so that the sound input can be immediately routed to the output without having to record it first?
  11. Hi @jpeyron, EDIT: I just tried programming another board (also zybo z7-10), and it worked. Maybe there was a problem connecting to my original board that caused this issue. I've installed Vivado 2016.4, and I was able to get a bitstream for the HDMI demo in under 30 minutes. I'm able to program the FPGA, but I'm having trouble programming the ARM core. When I try to run the debugger, I get one of the following errors, none of which I can consistently recreate: Memory write error at 0xF8000118. Cannot flush JTAG server queue. FT_Read returned 0, expected 12 Memory read er
  12. Hi Jon, Thanks for the help, my laptop has an i7-7500U with 12GB of RAM, 2 cores at 2.7GHz. I only had one project running on Vivado. Is there a reason why the bitstream takes that much longer in the newer version of Vivado? The 1h generation time I got last night is usable, but obviously faster is better.
  13. Hi Jon, Thanks for the response, I checked the version number in system_bd.tcl and it was already set to 2017.3, I haven't had to change it. I was actually able to get the project to compile this morning, shortly after I posted my question and before you responded. It took about 3 hours to generate a bitstream, but it and the demo code both worked. Right now I'm compiling the same block diagram again, just to see if Vivado always takes this long, and it seems to be hanging again. Looking at the properties of the route_design step, it seems to get stuck at 75% for a very long time. Is
  14. I've been trying to get the Zybo Z7-10 HDMI demo (link) to run on my board, but I can't seem to be able to compile the actual project (using Vivado 2017.3 on Windows 10). I created the project from the create_project.tcl script in the proj folder, and was able to generate the block diagram and wrapper. I upgraded the IP cores and verified that the xdc file was consistent with the wrapper. But when I try to generate a bistream, Vivado always seems to get stuck on route_design. I've left Vivado running for 4 hours and it still can't move past route_design, despite it still using ~30% of my CPU.
  15. I'm working with the HDMI ports on a Zybo Z7-10 development board, and I'm trying to set it up as an HDMI passthrough. As in, the HDMI input signal would simply be fed into the HDMI output port without any processing in between. I will eventually be filtering the video signal but I'm using this passthrough as a starting point. The HDMI hardware on my Zybo, as well as my HDMI source and output screen, are all confirmed working because I've been able to run Digilent's HDMI demo on it. I'm using Vivado 2017.3 I was able to get my block design started by following this forum post, replacing t