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newkid_old

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Topics posted by newkid_old

  1.  

    Question: Microblaze AXI GPIO Interrupt

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 12 answers
  2.  

    Question: CortexM3 on Arty100 Board

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 6 answers
  3.  

    Question: Arty100 Echo Server

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 6 answers
  4.  

    Question: Vivado 19.1 Echo Server Example

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 3 answers
  5.  

    Question: Arty Echo Server Example Memory

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 6 answers
  6.  

    Question: Arty Multiple Interrupt Problem

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 2 answers
  7.  

    Question: Output Port on IP Core

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 8 answers
  8.  

    Question: Constraining nets

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 1 answer
  9.  

    Question: Implementation Strategies

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 6 answers
  10.  

    Question: Simple Dual Port BRAM

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 3 answers
  11.  

    Question: Vivado not routing nets

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 17 answers
  12.  

    Question: AXI SPI

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 7 answers
  13.  

    Question: AXI Stream FIFO

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 10 answers
  14.  

    Question: Top Level Port error

    By newkid_old, in FPGA

    • Awaiting best answer
    • 0 votes
    • 3 answers
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