newkid_old

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Everything posted by newkid_old

  1. Jon, I downloaded the project and found that I had an older version of Vivado. I downloaded the newest version. I didn't realize its 2018.3 until I opened the project. Now I can't get the project I downloaded from you or my older projects to transmit a simple hello world. Any ideas?
  2. I am trying to implement an interrupt routine on my Arty board. I want to use the switches on the board to generate the interrupt. Here is my design: I used the example code that Xilinx offers and here is my code. At start up I initialize my IO and then my interrupt. Sometimes when the EnableExceptions function is called the program will jump to the interrupt vector but it locks up there. Most of the time however the interrupt setup is run and the while() loop in my main program works but the interrupt won't trigger with the switch. Any help is greatly appreciated. helloworld.c
  3. newkid_old

    Constraining nets

    I have an LVDS pair that I bring to a IBUFDS which then feeds my SelectIO module. Implementation is report a timing hold error. Does anyone know how to constrain this net to it corresponding data clock? This particular module has a data clock that feeds it for deserialization and I would have thought Vivado would know to use that clock but based off of the error that's not true.
  4. Thanks for the input. I will try different combinations of Synthesis strategies and Implementation strategies. This is my first major project with FPGAs. A couple questions came up in reading both of your posts: 1. Where do I find the "Register Balancing" option? 2. My design was originally a single channel design for testing but now its going to multiple channels with the same logic re-used. Is there a strategy that targets the re-use of logic? Cheers
  5. I have a design that fails timing with a negative THS as well as 1 of my nets not being routed. I use the default strategy. In reading in the Xilinx forums I see that you can choose other strategies so my question is if I change my strategy is it possible my design will succeed in timing and route my net?
  6. Thanks for the information. I will give it a try. Cheers, Curt
  7. newkid_old

    Simple Dual Port BRAM

    Can someone give some advice on the workings of the Simple Dual Port BRAM? I'm using channel A to store data thats coming from my ADC and channel B to read into my Microblaze processor. On the first pass it works (I verify by means of a known value coming out of the ADC) but subsequent passes the BRAM doesn't seem to read the new values coming out of the ADC. I've included a screenshot of how the BRAM is hooked up. I'm using an AXI GPIO to toggle the (Read/Write) pin on the BRAM as well as the address generator. I've also included my SDK program. Any help is appreciated. Cheers, Curt BRAM_Synch.txt
  8. newkid_old

    AXI SPI

    TI's LMH6681 Op amp is my target device. I am designing a board for my company that will use 3 of them. I picked up the CMOD to see if I could just talk to one for starters.
  9. newkid_old

    AXI SPI

    I'm using 2017.3
  10. newkid_old

    AXI SPI

    I'm using the CMOD-A7. I've mapped the signals to the JA header.
  11. newkid_old

    AXI SPI

    Has anyone been able to get the chip select output on the AXI SPI block working? I've tried the example code and other things I've found on line but no such luck. I've even tried different outputs from the block thinking it was just labelled wrong. ConfigPtr = XSpi_LookupConfig(TI_Amp); if (ConfigPtr == NULL) { xil_printf("Device not found\n\r"); } else { xil_printf("Found SPI module\n\r"); } delay(1000); Status = XSpi_CfgInitialize(&Spi, ConfigPtr, ConfigPtr->BaseAddress); //Status = XSpi_Initialize(&Spi, TI_Amp); if (Status != XST_SUCCESS) { xil_printf("SPI failed config\n\r"); } else { xil_printf("SPI config set\n\r"); XSpi_Reset(&Spi); //Stop the device if already on } delay(1000); Status = XSpi_SelfTest(&Spi); if (Status == XST_SUCCESS) { xil_printf("SPI self test passed\n\r"); } else if(Status == XST_REGISTER_ERROR) { xil_printf("SPI failed to write to register\n\r"); } else if(Status == XST_LOOPBACK_ERROR) { xil_printf("SPI failed loopback\n\r"); } delay(10); while(Status != XST_SUCCESS) { Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | XSP_LOOPBACK_OPTION | XSP_MANUAL_SSELECT_OPTION); } delay(10); XSpi_Start(&Spi); XSpi_IntrGlobalDisable(&Spi); while(1) { xil_printf("Hello World\n\r"); //XSpi_WriteReg(SPI_BASEADDR, 0x03, 0x50); //Writes to address 0x50 //a value of 6 //XSpi_Transfer(&Spi, writeBuffer, readBuffer, 1); XSpi_WriteReg(&Spi, 0x03, 0x50); delay(10000); readValue = 5; xil_printf("%u\n\r", readBuffer[0]); } Here's my code. I can see the SPI_Out and SPI_CLK lines doing there job but not the SS_0 line which is supposed to be the chip select. Any help is greatly appreciated.
  12. newkid_old

    AXI Stream FIFO

    The FIFO has a 100mhz clock on it. The adc is generating a new word at 5mhz currently. My counter is set to 512 which equates to a packet every 102uS. This assumes I'm understanding that a packet is the number of words it stores before a packet flag is generated.
  13. newkid_old

    AXI Stream FIFO

    80Mhz is my target speed.
  14. newkid_old

    AXI Stream FIFO

    I have an ADC that outputs a new number on the rising edge of a clock. I want to store x number of samples, for now say 128, then read them into my Microblaze and spit them out over UART.
  15. newkid_old

    AXI Stream FIFO

    I suppose I should have framed this as a question. Whats the best method to clock data in to a storage device? Xilinx has a few choices and I'm not sure which is the best.
  16. newkid_old

    AXI Stream FIFO

    I am trying to read data into a AXI streaming FIFO. I've attached my design. The data is presented on the axi_str_rxd_tdata. My clock that frames the data is applied to the axi_str_rxd_tvalid input. I have a counter that counts up to 128 and when the limit is reached it pulses the axi_str_rxd_tlast line. I am trying to read this data in my MicroBlaze processor but the only seem to catch one point of data. The first word is the data I'm feeding the FIFO but the next 127 words are zero. I am using Xilinx SDK example code for the fifo interaction. Any help is greatly appreciated. Cheers
  17. Thanks for the catch on the channel flop.
  18. newkid_old

    Top Level Port error

    I'm trying to implement a DDR output module that will serve as my ADC simulator. I have synthesized design but received this error when trying to implement: [Opt 31-1] OBUFDS design_1_i/util_ds_buf_0/U0/USE_OBUFDS.GEN_OBUFDS[0].OBUFDS_I O pin is not connected to a top-level port. Can anyone point me in a direction to fix this issue please?
  19. I wanted to add this post(rather a long time I know) that I have found a solution to my problem. My original intent was to read, using LVDS, a TI3423 development board from the Digilient Arty board. Utilizing the PMOD header I was able to connect and read values from the ADC. Here are the details so that anyone wanting to do the same thing can benefit from my journey through Xilinx hell. Using Xilinx Vivado I used a SelectIO IP block. I then set the input to DDR and 2 lanes at 6 bits per lane and changed the input points to differential LVDS25. Since the bank is 3.3Vdc the differential input voltage can be seen on the inputs as long as you use 50ohm resistors across the P/N pairs. I used a small bread board where my resistors reside. The key to the data was the frame clock which frames the data. Xilinx does not mention how to use this clock and only by extensive searching their forums did I find a guru who states the frame clock can be used on the div_clk_in. On the SelectIO block IP under the clocks tab you have to change the clock to internal which will enable the div_clk_in input. This is where you land the frame clock. The SelectIO block expects differential inputs for the data but only wants single ended inputs for the clock and the frame. I had to place Utility Buffers under the Base IP catalog to bring in differential inputs from the ADC. To read the data I used the Microblaze uC, uart and 2 axi gpio ip blocks. I monitor the the frame clock and when it changes states I read the 12 bit word and transfer it out over uart. Cheers, Curt
  20. For my test on my prototype board 1 Mhz is my target speed.
  21. Thanks for your help in finding the cause. Any ideas how I can constrain these signals so that they can make it from the elaborated design to the implemented design? Since I'm testing this out on an Arty board, my plan was / is to bring these 3 inputs to the PMOD B header of that board(document states its high speed). In the IO planner I've assigned these signals to package pins but still get the same error. Thanks, Curt
  22. Here is the screen shots I took of the elaboration. 1. is the over all design. 2. is the inside my IP block highlighting my signal that gets destroyed once it hits the implement stage and 3. Is the second signal that gets destroyed. I have done more tinkering to see what will work on my code and I've added this: attribute equivalent_register_removal: string; attribute equivalent_register_removal of BDX : signal is "no"; attribute equivalent_register_removal of BFSX : signal is "no"; attribute dont_touch:string; attribute dont_touch of BDX :signal is "true"; attribute dont_touch of BFSX :signal is "true"; Now my synthesis will add an IBUF to my two signals and implementation gives me an error of which I've added a screen shot:
  23. Here's an update to my situation. I added a KEEP attribute to my VHDL code after reading about nets not being routed on fpgadeveloper.net. This addition allowed my net to be routed from my outside port to the edge of my block IP. Inside the block IP it is routed no where else. This is only true in the schematic generated by the synthesis tool. In the implement tool it gives the same results where it shows my ports but no routing. Does this information help?
  24. Hi jpeyron, Thanks for the pointer to your working IP. After looking at it I'm pretty sure I did the same thing except I changed the port names to something slightly different so I could track it better in the process. I have a feeling that the two nets not be routed are a function of some setting I haven't read about. The odd thing is that synthesis and implementation both state they have done a successful job. I'm attaching the two pictures of the schematic that is generated by the implementation process. You can see my two ports but but nothing routed from them into my core, but the BCLKX signal gets buffered and routed.