newkid_old

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Everything posted by newkid_old

  1. Jon, Thanks for the reply. I am using the Digilent board files for my project. I am using the example Ethernet Echo Server that does work without my extra input on the interrupt controller. This is hooked to the 3rd input on that IP. The other two are as per the example which is the timer and the ethernet IP blocks interrupt. I've tried changing the Interrupt type from Level to Edge but get the same results. Thanks, Curt
  2. I have an issue with one of my Arty interrupts. I'm using the AXI GPIO interrupt along with the ethernet and timer interrupt(using the echo server example). I've placed some debug code that sends over the UART that the interrupt is recognized but it locks the Microblaze controller from there. void InterruptHandler(void *CallbackRef) { //dataReady = 1; //Signals the main loop that the FIFO is full and ready to be read xil_printf("Interrupt found... \n\r"); XGpio_InterruptClear(&fifoFull, XPAR_AXI_GPIO_0_IP2INTC_IRPT_MASK); XIntc_Acknowledge(XPAR_INTC_0_BASEADDR, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR); } Here's my interrupt handler code which works fine without any other interrupts. Here is my interrupt setup routine: void platform_setup_interrupts() { XIntc *intcp; intcp = &intc; XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID); XIntc_Start(intcp, XIN_REAL_MODE); XIntc_Connect(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR, (XInterruptHandler)InterruptHandler, &fifoFull); XIntc_Connect(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR, (XInterruptHandler)InterruptHandler, &fifoFull); XIntc_Enable(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR); /* Start the interrupt controller */ //XIntc_MasterEnable(XPAR_INTC_0_BASEADDR); XIntc_MasterEnable(XPAR_INTC_0_BASEADDR); #ifdef __PPC__ Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (XExceptionHandler)XIntc_DeviceInterruptHandler, (void*) XPAR_INTC_0_DEVICE_ID); #elif __MICROBLAZE__ microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp); #endif platform_setup_timer(); #ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK /* Enable timer and EMAC interrupts in the interrupt controller */ XIntc_EnableIntr(XPAR_INTC_0_BASEADDR, #ifdef __MICROBLAZE__ PLATFORM_TIMER_INTERRUPT_MASK | #endif XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK); #endif #ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID #ifdef __MICROBLAZE__ XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR); #endif XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID); #endif #ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR); XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID); #endif #ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID #ifdef __MICROBLAZE__ XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR); #endif XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID); #endif } I suspect an interrupt is being handled correctly but can't be for sure. Any help is greatly appreciated. Cheers
  3. If there is errors, I didn't see any and I do have my module running on an Art A7 board. I do register my Pulse_Out with the clock event in an IF statement. Here is my code: I changed the Pulse_Count to 8 bits which is different from the block seen above that's 16 bit. Any pointers are appreciated. entity Pulse_Trigger is Port ( Reset : in STD_LOGIC; Clk : in std_logic; Trigger : in std_logic; Pulse_Length : in STD_LOGIC_VECTOR (7 downto 0); Pulse : out STD_LOGIC); end Pulse_Trigger; architecture Behavioral of Pulse_Trigger is signal count : std_logic_vector(7 downto 0); signal pulseon : std_logic; signal pulsetrig: std_logic; begin process(Reset, Clk, Trigger) begin if Reset = '1' then --reset logic Pulse <= '0'; pulseon <= '0'; pulsetrig <= '1'; count <= Pulse_Length; --load the current count into else if(Clk'event and Clk = '1' and Trigger = '1' and pulseon = '0' and pulsetrig = '1')then --Once the trigger pulse goes high latch pulseon <= '1'; --buffer that mirrors the output Pulse <= '1'; --fire the pulse pulsetrig <= '0'; end if; if(Clk'event and Clk = '1' and pulseon = '1')then count <= unsigned(count) - '1'; end if; if(count = "00000000" and pulseon = '1')then Pulse <= '0'; --fire the pulse pulseon <= '0'; --buffer that mirrors the output end if; if(pulseon = '0' and Trigger = '0' and pulsetrig = '0')then --The pulse length has timed and the trigger has gone low pulsetrig <= '1'; end if; end if; end process; end Behavioral;
  4. I found a solution to this issue but not using the ILA module. I found this setting in the Synthesis tab in the settings called "keep equivalent registers". Clicked this setting and rerun the synthesis. It was deleting my Pulse_Length(15:0) input for some reason and this setting keeps it. Hopefully this bit of knowledge will help someone. Cheers, Curt
  5. Jon, Thanks for the pointer on the ILA. Whereas I wasn't able to get the module running in my block design I was able to find my problem. The simulation ran fine for my IP but when I tried the Implemented Simulator, I'm seeing exactly what I see on my o-scope which is a 12nS pulse. I have no experience in troubleshooting between simulator and implemented design. Any suggestions? Cheers
  6. I created a custom IP block that has some inputs and an output. I've ran the logic through the simulator and confirmed that everything is working as expected. I've packaged the custom block and added to the Arty A7 board. I've tied the output of my module to an physical output of the Arty (PMOD A pint to be precise). My problem is that I get no output from my module. I look at the signal with my oscope and see what looks to be a 80mV pulse where there should be a 3.3v pulse. Any help or clue as to why I'm not seeing my output would greatly be appreciated? Cheers
  7. Jon, I downloaded the project and found that I had an older version of Vivado. I downloaded the newest version. I didn't realize its 2018.3 until I opened the project. Now I can't get the project I downloaded from you or my older projects to transmit a simple hello world. Any ideas?
  8. I am trying to implement an interrupt routine on my Arty board. I want to use the switches on the board to generate the interrupt. Here is my design: I used the example code that Xilinx offers and here is my code. At start up I initialize my IO and then my interrupt. Sometimes when the EnableExceptions function is called the program will jump to the interrupt vector but it locks up there. Most of the time however the interrupt setup is run and the while() loop in my main program works but the interrupt won't trigger with the switch. Any help is greatly appreciated. helloworld.c
  9. newkid_old

    Constraining nets

    I have an LVDS pair that I bring to a IBUFDS which then feeds my SelectIO module. Implementation is report a timing hold error. Does anyone know how to constrain this net to it corresponding data clock? This particular module has a data clock that feeds it for deserialization and I would have thought Vivado would know to use that clock but based off of the error that's not true.
  10. Thanks for the input. I will try different combinations of Synthesis strategies and Implementation strategies. This is my first major project with FPGAs. A couple questions came up in reading both of your posts: 1. Where do I find the "Register Balancing" option? 2. My design was originally a single channel design for testing but now its going to multiple channels with the same logic re-used. Is there a strategy that targets the re-use of logic? Cheers
  11. I have a design that fails timing with a negative THS as well as 1 of my nets not being routed. I use the default strategy. In reading in the Xilinx forums I see that you can choose other strategies so my question is if I change my strategy is it possible my design will succeed in timing and route my net?
  12. Thanks for the information. I will give it a try. Cheers, Curt
  13. newkid_old

    Simple Dual Port BRAM

    Can someone give some advice on the workings of the Simple Dual Port BRAM? I'm using channel A to store data thats coming from my ADC and channel B to read into my Microblaze processor. On the first pass it works (I verify by means of a known value coming out of the ADC) but subsequent passes the BRAM doesn't seem to read the new values coming out of the ADC. I've included a screenshot of how the BRAM is hooked up. I'm using an AXI GPIO to toggle the (Read/Write) pin on the BRAM as well as the address generator. I've also included my SDK program. Any help is appreciated. Cheers, Curt BRAM_Synch.txt
  14. newkid_old

    AXI SPI

    TI's LMH6681 Op amp is my target device. I am designing a board for my company that will use 3 of them. I picked up the CMOD to see if I could just talk to one for starters.
  15. newkid_old

    AXI SPI

    I'm using 2017.3
  16. newkid_old

    AXI SPI

    I'm using the CMOD-A7. I've mapped the signals to the JA header.
  17. newkid_old

    AXI SPI

    Has anyone been able to get the chip select output on the AXI SPI block working? I've tried the example code and other things I've found on line but no such luck. I've even tried different outputs from the block thinking it was just labelled wrong. ConfigPtr = XSpi_LookupConfig(TI_Amp); if (ConfigPtr == NULL) { xil_printf("Device not found\n\r"); } else { xil_printf("Found SPI module\n\r"); } delay(1000); Status = XSpi_CfgInitialize(&Spi, ConfigPtr, ConfigPtr->BaseAddress); //Status = XSpi_Initialize(&Spi, TI_Amp); if (Status != XST_SUCCESS) { xil_printf("SPI failed config\n\r"); } else { xil_printf("SPI config set\n\r"); XSpi_Reset(&Spi); //Stop the device if already on } delay(1000); Status = XSpi_SelfTest(&Spi); if (Status == XST_SUCCESS) { xil_printf("SPI self test passed\n\r"); } else if(Status == XST_REGISTER_ERROR) { xil_printf("SPI failed to write to register\n\r"); } else if(Status == XST_LOOPBACK_ERROR) { xil_printf("SPI failed loopback\n\r"); } delay(10); while(Status != XST_SUCCESS) { Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | XSP_LOOPBACK_OPTION | XSP_MANUAL_SSELECT_OPTION); } delay(10); XSpi_Start(&Spi); XSpi_IntrGlobalDisable(&Spi); while(1) { xil_printf("Hello World\n\r"); //XSpi_WriteReg(SPI_BASEADDR, 0x03, 0x50); //Writes to address 0x50 //a value of 6 //XSpi_Transfer(&Spi, writeBuffer, readBuffer, 1); XSpi_WriteReg(&Spi, 0x03, 0x50); delay(10000); readValue = 5; xil_printf("%u\n\r", readBuffer[0]); } Here's my code. I can see the SPI_Out and SPI_CLK lines doing there job but not the SS_0 line which is supposed to be the chip select. Any help is greatly appreciated.
  18. newkid_old

    AXI Stream FIFO

    The FIFO has a 100mhz clock on it. The adc is generating a new word at 5mhz currently. My counter is set to 512 which equates to a packet every 102uS. This assumes I'm understanding that a packet is the number of words it stores before a packet flag is generated.
  19. newkid_old

    AXI Stream FIFO

    80Mhz is my target speed.
  20. newkid_old

    AXI Stream FIFO

    I have an ADC that outputs a new number on the rising edge of a clock. I want to store x number of samples, for now say 128, then read them into my Microblaze and spit them out over UART.
  21. newkid_old

    AXI Stream FIFO

    I suppose I should have framed this as a question. Whats the best method to clock data in to a storage device? Xilinx has a few choices and I'm not sure which is the best.
  22. newkid_old

    AXI Stream FIFO

    I am trying to read data into a AXI streaming FIFO. I've attached my design. The data is presented on the axi_str_rxd_tdata. My clock that frames the data is applied to the axi_str_rxd_tvalid input. I have a counter that counts up to 128 and when the limit is reached it pulses the axi_str_rxd_tlast line. I am trying to read this data in my MicroBlaze processor but the only seem to catch one point of data. The first word is the data I'm feeding the FIFO but the next 127 words are zero. I am using Xilinx SDK example code for the fifo interaction. Any help is greatly appreciated. Cheers
  23. Thanks for the catch on the channel flop.
  24. newkid_old

    Top Level Port error

    I'm trying to implement a DDR output module that will serve as my ADC simulator. I have synthesized design but received this error when trying to implement: [Opt 31-1] OBUFDS design_1_i/util_ds_buf_0/U0/USE_OBUFDS.GEN_OBUFDS[0].OBUFDS_I O pin is not connected to a top-level port. Can anyone point me in a direction to fix this issue please?
  25. I wanted to add this post(rather a long time I know) that I have found a solution to my problem. My original intent was to read, using LVDS, a TI3423 development board from the Digilient Arty board. Utilizing the PMOD header I was able to connect and read values from the ADC. Here are the details so that anyone wanting to do the same thing can benefit from my journey through Xilinx hell. Using Xilinx Vivado I used a SelectIO IP block. I then set the input to DDR and 2 lanes at 6 bits per lane and changed the input points to differential LVDS25. Since the bank is 3.3Vdc the differential input voltage can be seen on the inputs as long as you use 50ohm resistors across the P/N pairs. I used a small bread board where my resistors reside. The key to the data was the frame clock which frames the data. Xilinx does not mention how to use this clock and only by extensive searching their forums did I find a guru who states the frame clock can be used on the div_clk_in. On the SelectIO block IP under the clocks tab you have to change the clock to internal which will enable the div_clk_in input. This is where you land the frame clock. The SelectIO block expects differential inputs for the data but only wants single ended inputs for the clock and the frame. I had to place Utility Buffers under the Base IP catalog to bring in differential inputs from the ADC. To read the data I used the Microblaze uC, uart and 2 axi gpio ip blocks. I monitor the the frame clock and when it changes states I read the 12 bit word and transfer it out over uart. Cheers, Curt