newkid_old

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newkid_old last won the day on January 15 2018

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  1. newkid_old

    Constraining nets

    I have an LVDS pair that I bring to a IBUFDS which then feeds my SelectIO module. Implementation is report a timing hold error. Does anyone know how to constrain this net to it corresponding data clock? This particular module has a data clock that feeds it for deserialization and I would have thought Vivado would know to use that clock but based off of the error that's not true.
  2. newkid_old

    Implementation Strategies

    Thanks for the input. I will try different combinations of Synthesis strategies and Implementation strategies. This is my first major project with FPGAs. A couple questions came up in reading both of your posts: 1. Where do I find the "Register Balancing" option? 2. My design was originally a single channel design for testing but now its going to multiple channels with the same logic re-used. Is there a strategy that targets the re-use of logic? Cheers
  3. newkid_old

    Implementation Strategies

    I have a design that fails timing with a negative THS as well as 1 of my nets not being routed. I use the default strategy. In reading in the Xilinx forums I see that you can choose other strategies so my question is if I change my strategy is it possible my design will succeed in timing and route my net?
  4. newkid_old

    Simple Dual Port BRAM

    Thanks for the information. I will give it a try. Cheers, Curt
  5. newkid_old

    Simple Dual Port BRAM

    Can someone give some advice on the workings of the Simple Dual Port BRAM? I'm using channel A to store data thats coming from my ADC and channel B to read into my Microblaze processor. On the first pass it works (I verify by means of a known value coming out of the ADC) but subsequent passes the BRAM doesn't seem to read the new values coming out of the ADC. I've included a screenshot of how the BRAM is hooked up. I'm using an AXI GPIO to toggle the (Read/Write) pin on the BRAM as well as the address generator. I've also included my SDK program. Any help is appreciated. Cheers, Curt BRAM_Synch.txt
  6. newkid_old

    AXI SPI

    TI's LMH6681 Op amp is my target device. I am designing a board for my company that will use 3 of them. I picked up the CMOD to see if I could just talk to one for starters.
  7. newkid_old

    AXI SPI

    I'm using 2017.3
  8. newkid_old

    AXI SPI

    I'm using the CMOD-A7. I've mapped the signals to the JA header.
  9. newkid_old

    AXI SPI

    Has anyone been able to get the chip select output on the AXI SPI block working? I've tried the example code and other things I've found on line but no such luck. I've even tried different outputs from the block thinking it was just labelled wrong. ConfigPtr = XSpi_LookupConfig(TI_Amp); if (ConfigPtr == NULL) { xil_printf("Device not found\n\r"); } else { xil_printf("Found SPI module\n\r"); } delay(1000); Status = XSpi_CfgInitialize(&Spi, ConfigPtr, ConfigPtr->BaseAddress); //Status = XSpi_Initialize(&Spi, TI_Amp); if (Status != XST_SUCCESS) { xil_printf("SPI failed config\n\r"); } else { xil_printf("SPI config set\n\r"); XSpi_Reset(&Spi); //Stop the device if already on } delay(1000); Status = XSpi_SelfTest(&Spi); if (Status == XST_SUCCESS) { xil_printf("SPI self test passed\n\r"); } else if(Status == XST_REGISTER_ERROR) { xil_printf("SPI failed to write to register\n\r"); } else if(Status == XST_LOOPBACK_ERROR) { xil_printf("SPI failed loopback\n\r"); } delay(10); while(Status != XST_SUCCESS) { Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | XSP_LOOPBACK_OPTION | XSP_MANUAL_SSELECT_OPTION); } delay(10); XSpi_Start(&Spi); XSpi_IntrGlobalDisable(&Spi); while(1) { xil_printf("Hello World\n\r"); //XSpi_WriteReg(SPI_BASEADDR, 0x03, 0x50); //Writes to address 0x50 //a value of 6 //XSpi_Transfer(&Spi, writeBuffer, readBuffer, 1); XSpi_WriteReg(&Spi, 0x03, 0x50); delay(10000); readValue = 5; xil_printf("%u\n\r", readBuffer[0]); } Here's my code. I can see the SPI_Out and SPI_CLK lines doing there job but not the SS_0 line which is supposed to be the chip select. Any help is greatly appreciated.
  10. newkid_old

    AXI Stream FIFO

    The FIFO has a 100mhz clock on it. The adc is generating a new word at 5mhz currently. My counter is set to 512 which equates to a packet every 102uS. This assumes I'm understanding that a packet is the number of words it stores before a packet flag is generated.
  11. newkid_old

    AXI Stream FIFO

    80Mhz is my target speed.
  12. newkid_old

    AXI Stream FIFO

    I have an ADC that outputs a new number on the rising edge of a clock. I want to store x number of samples, for now say 128, then read them into my Microblaze and spit them out over UART.
  13. newkid_old

    AXI Stream FIFO

    I suppose I should have framed this as a question. Whats the best method to clock data in to a storage device? Xilinx has a few choices and I'm not sure which is the best.
  14. newkid_old

    AXI Stream FIFO

    I am trying to read data into a AXI streaming FIFO. I've attached my design. The data is presented on the axi_str_rxd_tdata. My clock that frames the data is applied to the axi_str_rxd_tvalid input. I have a counter that counts up to 128 and when the limit is reached it pulses the axi_str_rxd_tlast line. I am trying to read this data in my MicroBlaze processor but the only seem to catch one point of data. The first word is the data I'm feeding the FIFO but the next 127 words are zero. I am using Xilinx SDK example code for the fifo interaction. Any help is greatly appreciated. Cheers
  15. newkid_old

    Top Level Port error

    Thanks for the catch on the channel flop.