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newkid_old last won the day on January 15 2018

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  1. I have downloaded the Arm CortexM3 package and have followed the steps for Vivado 20 and Vitis to recognize the repository. I'm able to generate a bitstream from Vivado but when I get to Vitis and create the Platform Project I get this error: I have found a post on the Xilinx forums where this was a known problem in Vivado 19.2 so I installed the newest version 20 and still have the same issue. Any help is greatly appreciated.
  2. My apologies. I misinterpreted your question. When I was running the echo server in Vivado 18.3 I got the full message in serial terminal concerning the IP address and port. Now that I'm using Vivado 19.2 and the new SDK Vitis, I get the message that I displayed in my original post. It seems that the IP address and port are never getting set.
  3. No. It would tell me the echo server had been setup at the default IP address and port. You could then open a telnet Putty window at that address and port and have it echo what you typed in the console.
  4. Yes. I've installed the board files and followed the example. I had the example running on Vivado 18.3.
  5. newkid_old

    Arty100 Echo Server

    I am trying to run the Echo Server demo on my Arty A7-100. I am using Vivado 19.2 and Vitis. I have the application loaded on the Arty and in my UART window it gives this message: It never gets to "TCP echo server started @ port 7". I've changed the TEMAC adapter speed to 100, 10 and Auto-Negotiate and all have the same problem. Any help is greatly appreciated. Cheers
  6. That fixed it. Thank you for your help. Cheers, Curt
  7. I have recently upgraded Xilinx Vivado to 19.1 and attempted to setup the Arty Echo Server example on my Arty A7-35 board. The bit stream gets generated without any errors as does the SDK portion of the project. After the bitstream and program is loaded onto the Arty however nothing happens. I receive nothing from the UART stating the server has started. I have successfully ran the echo server example when using Vivado 18.3. Has anyone else ran into this problem? Thanks in advance.
  8. Thank you for help on this.
  9. Thanks for you reply. Do you think the Arty a7-100 could handle the task?
  10. I'm wondering if there's a way to modify the Arty Echo Server example project to utilize BRAM on the FPGA vice the DDR chip on the board? Thanks in advance.
  11. Jon, Thanks for the reply. I am using the Digilent board files for my project. I am using the example Ethernet Echo Server that does work without my extra input on the interrupt controller. This is hooked to the 3rd input on that IP. The other two are as per the example which is the timer and the ethernet IP blocks interrupt. I've tried changing the Interrupt type from Level to Edge but get the same results. Thanks, Curt
  12. I have an issue with one of my Arty interrupts. I'm using the AXI GPIO interrupt along with the ethernet and timer interrupt(using the echo server example). I've placed some debug code that sends over the UART that the interrupt is recognized but it locks the Microblaze controller from there. void InterruptHandler(void *CallbackRef) { //dataReady = 1; //Signals the main loop that the FIFO is full and ready to be read xil_printf("Interrupt found... \n\r"); XGpio_InterruptClear(&fifoFull, XPAR_AXI_GPIO_0_IP2INTC_IRPT_MASK); XIntc_Acknowledge(XPAR_INTC_0_BASEADDR, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR); } Here's my interrupt handler code which works fine without any other interrupts. Here is my interrupt setup routine: void platform_setup_interrupts() { XIntc *intcp; intcp = &intc; XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID); XIntc_Start(intcp, XIN_REAL_MODE); XIntc_Connect(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR, (XInterruptHandler)InterruptHandler, &fifoFull); XIntc_Connect(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR, (XInterruptHandler)InterruptHandler, &fifoFull); XIntc_Enable(intcp, XPAR_MICROBLAZE_0_AXI_INTC_AXI_GPIO_0_IP2INTC_IRPT_INTR); /* Start the interrupt controller */ //XIntc_MasterEnable(XPAR_INTC_0_BASEADDR); XIntc_MasterEnable(XPAR_INTC_0_BASEADDR); #ifdef __PPC__ Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (XExceptionHandler)XIntc_DeviceInterruptHandler, (void*) XPAR_INTC_0_DEVICE_ID); #elif __MICROBLAZE__ microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp); #endif platform_setup_timer(); #ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK /* Enable timer and EMAC interrupts in the interrupt controller */ XIntc_EnableIntr(XPAR_INTC_0_BASEADDR, #ifdef __MICROBLAZE__ PLATFORM_TIMER_INTERRUPT_MASK | #endif XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK); #endif #ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID #ifdef __MICROBLAZE__ XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR); #endif XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID); #endif #ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR); XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID); #endif #ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID #ifdef __MICROBLAZE__ XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR); #endif XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID); #endif } I suspect an interrupt is being handled correctly but can't be for sure. Any help is greatly appreciated. Cheers
  13. If there is errors, I didn't see any and I do have my module running on an Art A7 board. I do register my Pulse_Out with the clock event in an IF statement. Here is my code: I changed the Pulse_Count to 8 bits which is different from the block seen above that's 16 bit. Any pointers are appreciated. entity Pulse_Trigger is Port ( Reset : in STD_LOGIC; Clk : in std_logic; Trigger : in std_logic; Pulse_Length : in STD_LOGIC_VECTOR (7 downto 0); Pulse : out STD_LOGIC); end Pulse_Trigger; architecture Behavioral of Pulse_Trigger is signal count : std_logic_vector(7 downto 0); signal pulseon : std_logic; signal pulsetrig: std_logic; begin process(Reset, Clk, Trigger) begin if Reset = '1' then --reset logic Pulse <= '0'; pulseon <= '0'; pulsetrig <= '1'; count <= Pulse_Length; --load the current count into else if(Clk'event and Clk = '1' and Trigger = '1' and pulseon = '0' and pulsetrig = '1')then --Once the trigger pulse goes high latch pulseon <= '1'; --buffer that mirrors the output Pulse <= '1'; --fire the pulse pulsetrig <= '0'; end if; if(Clk'event and Clk = '1' and pulseon = '1')then count <= unsigned(count) - '1'; end if; if(count = "00000000" and pulseon = '1')then Pulse <= '0'; --fire the pulse pulseon <= '0'; --buffer that mirrors the output end if; if(pulseon = '0' and Trigger = '0' and pulsetrig = '0')then --The pulse length has timed and the trigger has gone low pulsetrig <= '1'; end if; end if; end process; end Behavioral;
  14. I found a solution to this issue but not using the ILA module. I found this setting in the Synthesis tab in the settings called "keep equivalent registers". Clicked this setting and rerun the synthesis. It was deleting my Pulse_Length(15:0) input for some reason and this setting keeps it. Hopefully this bit of knowledge will help someone. Cheers, Curt